Automatic Defect Classification System in Semiconductors EDS Test Based on System Entity Structure Methodologyopen access
- Authors
- Han, Young-Shin; Kim, SoYoung; Kim, TaeKyu; Jung, Jason J.
- Issue Date
- Jul-2010
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- semiconductor; system entity structure; electrical die sorting; fail bit map data; pruning
- Citation
- IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E93D, no.7, pp 2001 - 2004
- Pages
- 4
- Journal Title
- IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
- Volume
- E93D
- Number
- 7
- Start Page
- 2001
- End Page
- 2004
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/37759
- DOI
- 10.1587/transinf.E93.D.2001
- ISSN
- 0916-8532
- Abstract
- We exploit a structural knowledge representation scheme called System Entity Structure (SES) methodology to represent and manage wafer failure patterns which can make a significant influence to FABs in the semiconductor industry. It is important for the engineers to simulate various system verification processes by using predefined system entities (e.g., decomposition, taxonomy, and coupling relationships of a system) contained in the SES. For better computational performance, given a certain failure pattern, a Pruned SES (PES) can be extracted by selecting the only relevant system entities from the SES. Therefore, the SES-based simulation system allows the engineers to efficiently evaluate and monitor semiconductor data by i) analyzing failures to find out the corresponding causes and ii) managing historical data related to such failures.
- Files in This Item
-
- Appears in
Collections - College of Software > School of Computer Science and Engineering > 1. Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.