https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/331 Sat, 04 Apr 2026 17:22:40 GMT 2026-04-04T17:22:40Z https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/127336 Title: Overlay deviation caused by mask heating during EUV exposure Authors: Kang, Ji-won; Ko, Heechang; Kim, Minwoo; Chae, Yu-jin; Oh, Hyekeun; Son, Seung-woo Abstract: As the resolution of EUV lithography continues to improve, the allowable overlay tolerance has decreased to the sub-nanometer level, increasing the significance of mask thermal behavior on process stability. However, the measured overlay used for correction in actual processes includes the combined influence of mask heating, optical system aberrations, stage motion, and alignment errors, making it difficult to isolate the direct contribution of mask heating. To overcome this limitation, the thermo-mechanical response of the mask during exposure was modeled independently through simulation and translated into the corresponding wafer overlay. The temporal and spatial evolution of mask temperature and deformation during repeated exposures was analyzed, and the overlay magnitude and distribution were compared under various exposure conditions, including pattern type, dose, and numerical aperture (NA). Under the 0.55 NA condition, pronounced layer-to-layer errors were observed at in-die stitching regions where adjacent half-fields meet. These results indicate that mask heating is one of the dominant sources of overlay variation in high-resolution EUV lithography processes. © 2025 SPIE. All rights reserved. Sat, 01 Nov 2025 00:00:00 GMT https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/127336 2025-11-01T00:00:00Z https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/127335 Title: Source optimization for less aggressive optical proximity correction in 0.55 NA logic single patterning Authors: Kim, Minwoo; Chae, Yu-jin; Ko, Heechang; Kang, Ji-won; Yeung, Michael S.; Oh, Hyekeun; Son, Seung-woo Abstract: Logic metal layers, consisting of randomly arranged metal lines with various pitches, are intended to be printed by EUV single exposure. However, when such layers are exposed using a simple source, differences in pattern density and shape cause significant critical dimension (CD) variation, preventing the printed features from matching the target design. Moreover, the complexity of optical proximity correction (OPC) increases with pattern diversity and reduced feature size, resulting in higher computational cost and more challenging mask fabrication. In this study, we investigate the potential of pixelated source optimization to achieve high-fidelity patterning of logic metal layers without any use of OPC or bias. The optimized source is evaluated for different absorbers under 0.55 NA conditions. By comparing optimal source shapes for each absorber, we demonstrate that pixelated sources can reproduce the intended patterns while achieving high normalized image log slope (NILS) and a wide process window. This approach offers a pathway toward less aggressive OPC and improved manufacturability for future logic single patterning. © 2025 SPIE. All rights reserved. Sat, 01 Nov 2025 00:00:00 GMT https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/127335 2025-11-01T00:00:00Z https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/127358 Title: Pixelated source polarization optimization for hyper-NA EUV lithography Authors: Chae, Yu-jin; Kim, Minwoo; Kang, Ji-won; Ko, Heechang; Son, Seung-woo; Yeung, Michael S.; Oh, Hyekeun Abstract: As extreme ultraviolet (EUV) lithography advances into the hyper-numerical aperture (hyper-NA, NA > 0.75) regime, achieving sub-8 nm resolution while maintaining a sufficient process window (PW) becomes increasingly critical for enabling next-generation semiconductor nodes. According to the latest scaling roadmaps, metal pitches are expected to shrink below 16 nm, driving the need for advanced lithographic techniques that overcome the limitations of conventional polarized illumination methods. Although transverse electric (TE) and transverse magnetic (TM) polarization approaches have shown effectiveness in high-NA systems down to 15 nm pitch, their impact saturates as vectorial light–matter interactions become more dominant. To address these challenges, we present a pixelated source polarization optimization (SPO) technique tailored for hyper-NA EUV lithography. This method enables spatially resolved polarization control at each pixel within the source pupil, expanding the degrees of freedom beyond conventional uniform-polarization schemes. Rigorous electromagnetic simulations using the Fastlitho platform demonstrate that pixelated SPO extends resolution capabilities beyond previous limits, achieving 11 nm pitch for line-space (L/S) and 15 nm pitch for contact-hole (C/H) patterns—while maintaining peak normalized image log-slope (NILS) > 2.0 and robust normalized depth of focus (nDOF) across X and Y directions. Beyond resolution improvement, pixelated SPO simultaneously enhances NILS and DOF, thereby expanding process margins and ensuring patterning feasibility for complex DRAM and logic layouts. Previous results also confirm consistent CD control and lithographic success for mixed-pattern DRAM configurations incorporating L/S, diagonal, and C/H arrays. This study establishes pixelated SPO not only as an enhancement technique, but as a foundational enabler for future hyper-NA nodes, potentially supporting beyond-A2 scaling as projected in the ASML/imec roadmap. By pushing resolution boundaries while preserving process stability and pattern fidelity, pixelated SPO opens a new design space for advanced memory and logic device generations. Sat, 01 Nov 2025 00:00:00 GMT https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/127358 2025-11-01T00:00:00Z https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/127357 Title: Image twist and placement error during EUV exposure Authors: Ko, Heechang; Kang, Ji-won; Kim, Minwoo; Chea, Yu-jin; Oh, Hyekeun; Son, Seung-woo Abstract: In extreme ultra-violet (EUV) lithography, the local critical dimension uniformity (LCDU) and placement error are major contributors to edge placement error (EPE) budgets, thereby exerting a significant influence on product yield. During exposure, transient thermal deformation of the resist and underlying layers induces time-varying image blur, which deteriorates aerial image contrast and shifts the effective image centroid. Consequently, local PE accumulates across the exposure field, degrading global overlay accuracy. In this study, the coupled thermal–mechanical response of the resist on top of the wafer during scanning exposure is simulated under ASML NXE:3400B scanner conditions to quantitatively evaluate the relationship between deformation-induced image twist and pattern placement deviation. The proposed simulation framework enables correlation of local image degradation with field-scale overlay behavior. The results reveal that the transient in-plane deformation occurring during exposure induces orientation-dependent image twist along both the x- and y-scan directions, whose magnitude varies with pattern type. Furthermore, a strong correlation is observed between the placement error and the temporal trend of deformation, highlighting how local dynamic distortion can propagate to global overlay deviations in high-NA lithography. (2025) Published by SPIE. Downloading of the abstract is permitted for personal use only. Sat, 01 Nov 2025 00:00:00 GMT https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/127357 2025-11-01T00:00:00Z