Low-Temperature Polysilicon Oxide Thin-Film Transistors with Coplanar Structure Using Six Photomask Steps Demonstrating High Inverter Gain of 264 V V-1
DC Field | Value | Language |
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dc.contributor.author | Jeong, Duk Young | - |
dc.contributor.author | Chang, Yeoungjin | - |
dc.contributor.author | Yoon, Won Gyeong | - |
dc.contributor.author | Do, Youngbin | - |
dc.contributor.author | Jang, Jin | - |
dc.date.available | 2020-04-06T07:38:58Z | - |
dc.date.created | 2020-04-02 | - |
dc.date.issued | 2020-04 | - |
dc.identifier.issn | 1438-1656 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/26451 | - |
dc.description.abstract | The low-temperature polysilicon oxide (LTPO) complementary metal-oxide-semiconductor (CMOS) thin-film transistors (TFTs) is fabricated by p-type low-temperature polysilicon (LTPS) TFT and n-type amorphous indium-gallium-zinc oxide (a-IGZO) TFT using coplanar structure. A double-stack SiO2 layer deposited by high temperature first and then low-temperature process is used as a gate insulator for LTPS TFT, leading to reduce the number of photomask steps. The p-channel LTPS TFT of the fabricated LTPO circuits exhibits the field-effect mobility (mu(FE)) and threshold voltage (V-TH) of 89.9 cm(2) (V s)(-1) and -5.5 V, respectively. However, the a-IGZO TFT exhibits the mu(FE) of 22.5 cm(2) (V s)(-1) and V-TH of -1.3 V. Both the LTPS TFT and a-IGZO TFT show excellent bias stability (Delta V-TH of <0.1 V) and zero hysteresis voltage, which reveals the excellent interface between gate insulator and semiconductor. The LTPO CMOS inverter exhibits a gain of 264.5 V V-1 and a high noise margin of 4.29 V, and a low noise margin of 3.69 V at V-DD of 8 V. Therefore, the LTPO TFT technology developed in this work can be a promising candidate for low cost, large-area manufacturing of display, and TFT electronics. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | WILEY-V C H VERLAG GMBH | - |
dc.relation.isPartOf | ADVANCED ENGINEERING MATERIALS | - |
dc.title | Low-Temperature Polysilicon Oxide Thin-Film Transistors with Coplanar Structure Using Six Photomask Steps Demonstrating High Inverter Gain of 264 V V-1 | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000512956700001 | - |
dc.identifier.doi | 10.1002/adem.201901497 | - |
dc.identifier.bibliographicCitation | ADVANCED ENGINEERING MATERIALS, v.22, no.4 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.scopusid | 2-s2.0-85079399669 | - |
dc.citation.title | ADVANCED ENGINEERING MATERIALS | - |
dc.citation.volume | 22 | - |
dc.citation.number | 4 | - |
dc.contributor.affiliatedAuthor | Chang, Yeoungjin | - |
dc.type.docType | Article; Early Access | - |
dc.subject.keywordAuthor | amorphous indium-gallium-zinc oxide | - |
dc.subject.keywordAuthor | blue laser annealing | - |
dc.subject.keywordAuthor | complementary metal-oxide-semiconductor | - |
dc.subject.keywordAuthor | coplanar thin-film transistor | - |
dc.subject.keywordAuthor | low-temperature polysilicon oxide | - |
dc.subject.keywordPlus | LASER DOPANT ACTIVATION | - |
dc.subject.keywordPlus | POLYCRYSTALLINE SILICON | - |
dc.subject.keywordPlus | FABRICATION | - |
dc.subject.keywordPlus | CRYSTALLIZATION | - |
dc.subject.keywordPlus | TRANSPARENT | - |
dc.subject.keywordPlus | TECHNOLOGY | - |
dc.subject.keywordPlus | FIELD | - |
dc.subject.keywordPlus | GLASS | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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