Algorithmic Advancements and a Comparative Investigation of Left and Right Looking Sparse LU Factorization on GPU Platform for Circuit Simulation
DC Field | Value | Language |
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dc.contributor.author | Lee, Wai-Kong | - |
dc.contributor.author | Achar, Ramachandra | - |
dc.date.accessioned | 2022-10-14T02:40:49Z | - |
dc.date.available | 2022-10-14T02:40:49Z | - |
dc.date.created | 2022-09-22 | - |
dc.date.issued | 2022-07 | - |
dc.identifier.issn | 2169-3536 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/85681 | - |
dc.description.abstract | Sparse LU factorization is a key tool in the solution of large linear set of algebraic equations encompassing a wide range of computing applications. Recent advances in this field exploit the massively parallel architecture of the GPUs via left-looking algorithm (LLA) and right-looking algorithm (RLA). In this paper, adaptive cluster mode is proposed to improve the state-of-the-art in LLA for GPU platforms. The proposed method takes into consideration of varying sparsity at different levels during cluster mode execution, to adaptively configure the GPU block size and the number of parallel columns. The new refinements for LLA are also integrated with the dynamic parallelism that is available in modern GPU architectures. The paper also provides a comprehensive performance comparison of the LLA and hybrid RLA along with state-of-the-art advances on the same GPU platform. The results indicate that, when implemented with similar refinements and on a same platform, LLA provides better performance compared to the hybrid-RLA. The results would be useful to the scientific community while making decision on adopting LLA or RLA algorithms for sparse LU factorization. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE ACCESS | - |
dc.title | Algorithmic Advancements and a Comparative Investigation of Left and Right Looking Sparse LU Factorization on GPU Platform for Circuit Simulation | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000836203100001 | - |
dc.identifier.doi | 10.1109/ACCESS.2022.3193785 | - |
dc.identifier.bibliographicCitation | IEEE ACCESS, v.10, pp.78993 - 79003 | - |
dc.description.isOpenAccess | Y | - |
dc.identifier.scopusid | 2-s2.0-85135755594 | - |
dc.citation.endPage | 79003 | - |
dc.citation.startPage | 78993 | - |
dc.citation.title | IEEE ACCESS | - |
dc.citation.volume | 10 | - |
dc.contributor.affiliatedAuthor | Lee, Wai-Kong | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Graphics processing units | - |
dc.subject.keywordAuthor | Sparse matrices | - |
dc.subject.keywordAuthor | Pipelines | - |
dc.subject.keywordAuthor | Parallel processing | - |
dc.subject.keywordAuthor | Mathematical models | - |
dc.subject.keywordAuthor | Integrated circuit modeling | - |
dc.subject.keywordAuthor | Indexes | - |
dc.subject.keywordAuthor | Circuit simulation | - |
dc.subject.keywordAuthor | GPU | - |
dc.subject.keywordAuthor | LU factorization | - |
dc.subject.keywordAuthor | multi-core | - |
dc.subject.keywordAuthor | parallel simulation | - |
dc.subject.keywordAuthor | sparse matrices | - |
dc.subject.keywordAuthor | SPICE | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Telecommunications | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Telecommunications | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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