8.4-to-16-bit resolution, 1-to-16 kHz bandwidth ADC with programmable-gain functionality for multi-sensor applications

Abstract

A resolution-reconfigurable, bandwidth-scalable analogue-to-digital converter (ADC) with programmable-gain (PG) functionality for a multi-sensor system, which encompasses various signals such as bio-signals and battery-level, is presented. In PG and low-power mode, a PG first-order noise-shaping (NS) successive-approximation register (SAR) ADC achieves 8.4-to-10.2-bit operating up to 16 kHz while providing a gain of 1/2/4. The PG NS SAR ADC can be reconfigured as an adder and a quantiser in a delta-sigma (Delta sigma) modulator enhancing the order of the modulator for high-resolution. The third-order Delta sigma modulator achieves 16.1 bits in a bandwidth of 1 kHz. The work is implemented in a 0.18 mu m CMOS process with a 1.8 V power supply.