Silicon Nanowire Charge Trapping Memory for Energy-Efficient Neuromorphic Computing
DC Field | Value | Language |
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dc.contributor.author | Ansari, Md. Hasan Raza | - |
dc.contributor.author | Kannan, Udaya Mohanan | - |
dc.contributor.author | El-Atab, Nazek | - |
dc.date.accessioned | 2023-08-28T00:42:18Z | - |
dc.date.available | 2023-08-28T00:42:18Z | - |
dc.date.created | 2023-08-25 | - |
dc.date.issued | 2023-07 | - |
dc.identifier.issn | 1536-125X | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/88893 | - |
dc.description.abstract | This work highlights the utilization of the floating body effect and charge-trapping/de-trapping phenomenon of a Silicon-nanowire (Si-nanowire) charge-trapping memory for an artificial synapse of neuromorphic computing application. Charge trapping/de-trapping in the nitride layer characterizes the long-term potentiation (LTP)/depression (LTD). The accumulation of holes in the potential well achieves short-term potentiation (STP) and controls the transition from STP to LTP. Also, the transition from STP to LTP is analyzed through gate length scaling and high-? material (Al2O3) for blocking oxide. Furthermore, the conductance values of the device are utilized for system-level simulation. System-level hardware parameters of a convolutional neural network (CNN) for inference applications are evaluated and compared to a static random-access memory (SRAM) device and charge-trapping memory. The results confirm that the Si-nanowire transistor with better gate controllability has a high retention time for LTP states, consumes low power, and archives better accuracy (91.27%). These results make the device suitable for low-power neuromorphic applications. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON NANOTECHNOLOGY | - |
dc.title | Silicon Nanowire Charge Trapping Memory for Energy-Efficient Neuromorphic Computing | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 001042033400001 | - |
dc.identifier.doi | 10.1109/TNANO.2023.3296673 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.22, pp.409 - 416 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.scopusid | 2-s2.0-85165269291 | - |
dc.citation.endPage | 416 | - |
dc.citation.startPage | 409 | - |
dc.citation.title | IEEE TRANSACTIONS ON NANOTECHNOLOGY | - |
dc.citation.volume | 22 | - |
dc.contributor.affiliatedAuthor | Kannan, Udaya Mohanan | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Si-nanowire | - |
dc.subject.keywordAuthor | gate all around (GAA) | - |
dc.subject.keywordAuthor | synaptic transistor | - |
dc.subject.keywordAuthor | short term potentiation (STP) | - |
dc.subject.keywordAuthor | long term potentiation (LTP) | - |
dc.subject.keywordAuthor | long term depression (LTD) | - |
dc.subject.keywordAuthor | neural network | - |
dc.subject.keywordAuthor | neuromorphic computing | - |
dc.subject.keywordPlus | SYNAPTIC DEVICE | - |
dc.subject.keywordPlus | 1T DRAM | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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