ScholarWorks@Gachon: Seo, MinJae

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Seo, MinJae (서민재)

반도체대학 (반도체·전자공학부)

Research Area: 혼성 신호 집적 회로 설계, 생체 신호 획득을 위한 저전력 회로 설계, 통신용 고속 아날로그-디지털 변화기 설계, Mixed-signal integrated circuit design, Low power circuit design for bio-medical signal acquisition, Analog-to-digital converter for communication system

Tel 031-750-5590
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successive approximation register (SAR):3||low power:3||Analogtodigital converter (ADC):3||delta (Delta) searching:2||Calibration:2||timeinterleaving:2||analogtodigital converter (ADC):2||Capacitance:1||Capacitor DAC:1||Circuits and systems:1||Clock generator:1||Clocks:1||DAC:1||DLL:1||Delays:1||Design methodology:1||Interpolation:1||MSBrounding:1||Multiplexing:1||Power demand:1||Prototypes:1||SAR ADC:1||SARassisted timeinterleaved SAR (SATISAR):1||Switches:1||Voltage:1||amorphous InSnZnO (aITZO):1||analog circuit synthesis:1||background calibration:1||calibration:1||calibrationfree:1||capacitive interpolation:1||capacitivelevel shifting:1||capacitorDAC (CDAC) compiler:1||continuoustime deltasigma modulator (CT DSM):1||deltareadout scheme:1||digital calibration:1||digitaldomain noise coupling (DNC):1||dualresidue:1||flash analogtodigital converter (ADC):1||fullscale referring calibration:1||gainboosting dynamic comparator:1||high speed and high resolution:1||highspeed interface:1||input buffer:1||interstage mismatch:1||loopembedded input buffer:1||low voltage:1||lowjitter clock:1||lownoise comparator:1||massive:1||memristor crossbar array:1||multiple delayed lockedloop:1||noise coupling:1||noiseshaping successiveapproximation register analogtodigital converter (SAR ADC):1||offset:1||offset calibration:1||openloop residue amplifier:1||oversampling:1||ovonic threshold switch (OTS):1||phasechange memory (PCM):1||phasedetector (PD):1||pipelinedSAR architecture:1||pushpull source follower (SF):1||selector device:1||sense amplifier (SA):1||skew:1||skewed NANDbased comparator:1||skipreset:1||skipreset (SR):1||standard cell:1||static phase offset:1||successive approximation register (SAR) ADC:1||successiveapproximation register (SAR):1||successiveapproximationregister (SAR):1||synthesizable:1||synthesizable bootstrapped switch:1||temperature drift:1||temperaturedependencycompensating readout scheme:1||timedomain interpolation:1||timeinterleaved:1||timeinterleaved ADC.:1||trilevel dataweight averaging (TDWA):1||trilevel split monotonic switching:1||twostep flash ADC:1||voltagetotime conversion:1||3D crosspoint structure:1||wide frequency range:1||Analogtodigital conversion:1||Ash:1||Asynchronous SAR ADC:1||Biopotential signal:1||CDAC linearity calibration:1||CMOS image sensor (CIS):1||

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1342, Seongnam-daero, Sujeong-gu, Seongnam-si, Gyeonggi-do, Republic of Korea(13120)031-750-5114

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