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Variable-Weight Block Dual-Diagonal Structure for Low-Rate QC LDPC Codes With Low Error Floors

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dc.contributor.authorPark, Hosung-
dc.contributor.authorKwak, Hee-Youl-
dc.contributor.authorHong, Seokbeom-
dc.contributor.authorNo, Jong-Seon-
dc.contributor.authorShin, Dong-Joon-
dc.date.accessioned2021-08-02T09:51:52Z-
dc.date.available2021-08-02T09:51:52Z-
dc.date.created2021-05-12-
dc.date.issued2020-03-
dc.identifier.issn0090-6778-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/10617-
dc.description.abstractIrregular quasi-cyclic (QC) low-density parity-check (LDPC) codes with the block dual-diagonal (BDD) parity structure are widely adopted in many communication standards because the BDD structure supports an efficient encoding and many degree-2 variable nodes inside are adequate for the construction of mid- to high-rate codes. However, we observe that low-rate irregular QC LDPC codes with the BDD parity structure inherently contain too many degree-2 variable nodes and suffer from error floors in high signal-to-noise ratio (SNR) region. In this paper, a generalized BDD structure including double-weight circulants as well as circulant permutation matrices is proposed for low-rate irregular QC LDPC codes with low error floors which is achieved with a little bit giving up error performance in the waterfall region. When constructing the parity part of a code with the generalized BDD structure, the portion of double-weight circulants is variable so that the resulting LDPC code can achieve a desired degree distribution including degrees 2 and 3 while supporting the efficient encoding. We show that low-rate QC LDPC codes constructed with the proposed BDD structure have better theoretical properties and lower error floor than those with the conventional BDD structure.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleVariable-Weight Block Dual-Diagonal Structure for Low-Rate QC LDPC Codes With Low Error Floors-
dc.typeArticle-
dc.contributor.affiliatedAuthorShin, Dong-Joon-
dc.identifier.doi10.1109/TCOMM.2019.2957474-
dc.identifier.scopusid2-s2.0-85082165582-
dc.identifier.wosid000522192600002-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON COMMUNICATIONS, v.68, no.3, pp.1344 - 1357-
dc.relation.isPartOfIEEE TRANSACTIONS ON COMMUNICATIONS-
dc.citation.titleIEEE TRANSACTIONS ON COMMUNICATIONS-
dc.citation.volume68-
dc.citation.number3-
dc.citation.startPage1344-
dc.citation.endPage1357-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaTelecommunications-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryTelecommunications-
dc.subject.keywordPlusPARITY-CHECK CODES-
dc.subject.keywordPlusMINIMUM DISTANCE-
dc.subject.keywordPlusUPPER-BOUNDS-
dc.subject.keywordPlusDESIGN-
dc.subject.keywordPlusCYCLES-
dc.subject.keywordAuthorParity check codes-
dc.subject.keywordAuthorEncoding-
dc.subject.keywordAuthorHamming distance-
dc.subject.keywordAuthorIndexes-
dc.subject.keywordAuthorElectronic mail-
dc.subject.keywordAuthorSignal to noise ratio-
dc.subject.keywordAuthorUpper bound-
dc.subject.keywordAuthorBlock dual-diagonal (BDD) structure-
dc.subject.keywordAuthorcirculant matrices-
dc.subject.keywordAuthorefficient encoding-
dc.subject.keywordAuthorerror floor-
dc.subject.keywordAuthorgirth-
dc.subject.keywordAuthorminimum Hamming distance-
dc.subject.keywordAuthorprotograph-
dc.subject.keywordAuthorquasi-cyclic (QC) low-density parity-check (LDPC) codes-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8922716-
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