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A Novel Program Operation Scheme With Negative Bias in 3-D nand Flash Memory
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Sim, Jae-Min | - |
| dc.contributor.author | Kang, Myounggon | - |
| dc.contributor.author | Song, Yun-Heub | - |
| dc.date.accessioned | 2022-07-06T11:06:06Z | - |
| dc.date.available | 2022-07-06T11:06:06Z | - |
| dc.date.issued | 2021-12 | - |
| dc.identifier.issn | 0018-9383 | - |
| dc.identifier.issn | 1557-9646 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/140177 | - |
| dc.description.abstract | In this article, we proposed a new program operation scheme to overcome the degradation of program window in scaling down of 3-D NAND( )flash memory. First, we investigated natural V-th shift (NVS) effect in scaled-down structure and confirmed that this effect occurs due to an increase in fringe field by adjacent read voltage. Second, we investigated programmed and erased V-th window with scaling down and confirmed that programmed and erased V-th is decreased significantly due to the NVS effect. To overcome this scaling effect, we proposed a new program operation scheme using negative bias. The proposed scheme not only improves the program window margin but also achieves voltage scaling. In addition, the proposed scheme enables multistring operation through improved self-boosting, which is a compatible scheme in full array level. | - |
| dc.format.extent | 6 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | Institute of Electrical and Electronics Engineers | - |
| dc.title | A Novel Program Operation Scheme With Negative Bias in 3-D nand Flash Memory | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.doi | 10.1109/TED.2021.3121648 | - |
| dc.identifier.scopusid | 2-s2.0-85118977082 | - |
| dc.identifier.wosid | 000724501000028 | - |
| dc.identifier.bibliographicCitation | IEEE Transactions on Electron Devices, v.68, no.12, pp 6112 - 6117 | - |
| dc.citation.title | IEEE Transactions on Electron Devices | - |
| dc.citation.volume | 68 | - |
| dc.citation.number | 12 | - |
| dc.citation.startPage | 6112 | - |
| dc.citation.endPage | 6117 | - |
| dc.type.docType | Article | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalResearchArea | Physics | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
| dc.subject.keywordPlus | Flash memory | - |
| dc.subject.keywordPlus | Memory architecture | - |
| dc.subject.keywordPlus | NAND circuits | - |
| dc.subject.keywordPlus | Voltage scaling | - |
| dc.subject.keywordPlus | 3-D nand flash memory | - |
| dc.subject.keywordPlus | Fringe fields | - |
| dc.subject.keywordPlus | NAND flash memory | - |
| dc.subject.keywordPlus | Natural vth shift | - |
| dc.subject.keywordPlus | Negative bias | - |
| dc.subject.keywordPlus | New projects | - |
| dc.subject.keywordPlus | Operation schemes | - |
| dc.subject.keywordPlus | Program operation | - |
| dc.subject.keywordPlus | Scaling down | - |
| dc.subject.keywordPlus | Self-boosting operation | - |
| dc.subject.keywordAuthor | 3-D nand flash memory | - |
| dc.subject.keywordAuthor | Ash | - |
| dc.subject.keywordAuthor | Dry etching | - |
| dc.subject.keywordAuthor | Electric potential | - |
| dc.subject.keywordAuthor | Electron traps | - |
| dc.subject.keywordAuthor | natural Vth shift (NVS) | - |
| dc.subject.keywordAuthor | negative bias | - |
| dc.subject.keywordAuthor | program operation | - |
| dc.subject.keywordAuthor | Reliability | - |
| dc.subject.keywordAuthor | scaling down | - |
| dc.subject.keywordAuthor | self-boosting operation. | - |
| dc.subject.keywordAuthor | Timing | - |
| dc.subject.keywordAuthor | Voltage | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/9610133 | - |
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