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TernGEMM: GEneral Matrix Multiply Library with Ternary Weights for Fast DNN Inference

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dc.contributor.authorChoi, Seokhyeon-
dc.contributor.authorShim, Kyuhong-
dc.contributor.authorChoi, Jungwook-
dc.contributor.authorSung, Wonyong-
dc.contributor.authorShim, Byonghyo-
dc.date.accessioned2022-07-06T11:33:47Z-
dc.date.available2022-07-06T11:33:47Z-
dc.date.created2022-01-26-
dc.date.issued2021-11-
dc.identifier.issn1520-6130-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/140385-
dc.description.abstractEfficient implementation of deep neural networks on CPU-based systems is very critical because applications proliferate to embedded and Internet of Things (IoT) systems. Many CPUs for personal computers and embedded systems equip Single Instruction Multiple Data (SIMD) instructions, which can be utilized to implement an efficient GEneral Matrix Multiply (GEMM) library that is very necessary for efficient deep neural network implementation. While many deep neural networks show quite good performance even at 1-bit or 2-bit precision, the current CPU instruction and library do not efficiently support arithmetic operations below 8-bit. We propose TernGEMM, a special GEMM library using SIMD instructions for Deep Neural Network (DNN) inference with ternary weights and activations under 8-bit. TernGEMM improves the speed by replacing slow multiply-add with logical operations and also accumulating a number of multiplications without bit expansion operations. We compared the speedup of TernGEMM with tiling optimization and GEMMLowp, an 8-bit precision GEMM library. For Intel CPU, the speedup of ×2.052, ×2.973, and ×2.986 is achieved on ResNet-50, MobileNet-V2, EfficientNet-B0, respectively. For ARM CPU, TernGEMM's speedup is ×2.143, ×1.765, and ×1.856, respectively.-
dc.language영어-
dc.language.isoen-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleTernGEMM: GEneral Matrix Multiply Library with Ternary Weights for Fast DNN Inference-
dc.typeArticle-
dc.contributor.affiliatedAuthorChoi, Jungwook-
dc.identifier.doi10.1109/SiPS52927.2021.00028-
dc.identifier.scopusid2-s2.0-85122863833-
dc.identifier.wosid000783958100020-
dc.identifier.bibliographicCitationIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, v.2021, no.October, pp.111 - 116-
dc.relation.isPartOfIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation-
dc.citation.titleIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation-
dc.citation.volume2021-
dc.citation.numberOctober-
dc.citation.startPage111-
dc.citation.endPage116-
dc.type.rimsART-
dc.type.docTypeProceedings Paper-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaTelecommunications-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryTelecommunications-
dc.subject.keywordPlusDeep neural networks-
dc.subject.keywordPlusEmbedded systems-
dc.subject.keywordPlusInternet of things-
dc.subject.keywordPlusPersonal computers-
dc.subject.keywordPlusProgram processors-
dc.subject.keywordPlusBit precision-
dc.subject.keywordPlusEfficient implementation-
dc.subject.keywordPlusEmbedded-system-
dc.subject.keywordPlusImplementation-
dc.subject.keywordPlusInference-
dc.subject.keywordPlusMAtrix multiplication-
dc.subject.keywordPlusMatrix multiply-
dc.subject.keywordPlusNetwork inference-
dc.subject.keywordPlusPerformance-
dc.subject.keywordPlusSingle instruction multiple data instructions-
dc.subject.keywordPlusMatrix algebra-
dc.subject.keywordAuthorDeep neural networks-
dc.subject.keywordAuthorImplementation-
dc.subject.keywordAuthorInference-
dc.subject.keywordAuthorMatrix multiplication-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/9605039-
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