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Effect of the Blocking Oxide Layer With Asymmetric Taper Angles in 3-D NAND Flash Memories

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dc.contributor.authorLee, Jun Gyu-
dc.contributor.authorJung, Woo Je-
dc.contributor.authorPark, Jae Hyeon-
dc.contributor.authorYoo, Keon-Ho-
dc.contributor.authorKim, Tae Whan-
dc.date.accessioned2022-07-06T14:35:29Z-
dc.date.available2022-07-06T14:35:29Z-
dc.date.created2021-11-22-
dc.date.issued2021-09-
dc.identifier.issn2168-6734-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/141132-
dc.description.abstractThe tapered channel effect is a major concern in three-dimensional (3-D) NAND technology because the effect causes differences in the electrical characteristics, including the threshold voltage (V-T), between the upper and the lower cells. We simulated the tapered channel effect by using Sentaurus technology, computer-aided design (TCAD) tools, and based on the results, we propose a novel method to lessen the non-uniformity of the threshold voltage shift (Delta V-T) between the cells. The difference in Delta V-T between the upper and the lower cells due to the tapered channel can be reduced by employing a tapered blocking oxide layer with a proper taper angle. These results will be helpful in designing reliable 3-D NAND flash memories.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleEffect of the Blocking Oxide Layer With Asymmetric Taper Angles in 3-D NAND Flash Memories-
dc.typeArticle-
dc.contributor.affiliatedAuthorKim, Tae Whan-
dc.identifier.doi10.1109/JEDS.2021.3104843-
dc.identifier.scopusid2-s2.0-85113238943-
dc.identifier.wosid000688215400001-
dc.identifier.bibliographicCitationIEEE Journal of the Electron Devices Society, v.9, pp.774 - 777-
dc.relation.isPartOfIEEE Journal of the Electron Devices Society-
dc.citation.titleIEEE Journal of the Electron Devices Society-
dc.citation.volume9-
dc.citation.startPage774-
dc.citation.endPage777-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusGRAIN-BOUNDARY TRAPS-
dc.subject.keywordPlusTHICKNESS-
dc.subject.keywordPlusSIZE-
dc.subject.keywordAuthorFlash memories-
dc.subject.keywordAuthorLogic gates-
dc.subject.keywordAuthorElectron traps-
dc.subject.keywordAuthorThreshold voltage-
dc.subject.keywordAuthorTools-
dc.subject.keywordAuthorProgramming-
dc.subject.keywordAuthorLicenses-
dc.subject.keywordAuthor3-D NAND flash memories-
dc.subject.keywordAuthorthreshold voltage shift-
dc.subject.keywordAuthortapered channel-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/9514533-
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