Effect of the Blocking Oxide Layer With Asymmetric Taper Angles in 3-D NAND Flash Memories
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Jun Gyu | - |
dc.contributor.author | Jung, Woo Je | - |
dc.contributor.author | Park, Jae Hyeon | - |
dc.contributor.author | Yoo, Keon-Ho | - |
dc.contributor.author | Kim, Tae Whan | - |
dc.date.accessioned | 2022-07-06T14:35:29Z | - |
dc.date.available | 2022-07-06T14:35:29Z | - |
dc.date.created | 2021-11-22 | - |
dc.date.issued | 2021-09 | - |
dc.identifier.issn | 2168-6734 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/141132 | - |
dc.description.abstract | The tapered channel effect is a major concern in three-dimensional (3-D) NAND technology because the effect causes differences in the electrical characteristics, including the threshold voltage (V-T), between the upper and the lower cells. We simulated the tapered channel effect by using Sentaurus technology, computer-aided design (TCAD) tools, and based on the results, we propose a novel method to lessen the non-uniformity of the threshold voltage shift (Delta V-T) between the cells. The difference in Delta V-T between the upper and the lower cells due to the tapered channel can be reduced by employing a tapered blocking oxide layer with a proper taper angle. These results will be helpful in designing reliable 3-D NAND flash memories. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Effect of the Blocking Oxide Layer With Asymmetric Taper Angles in 3-D NAND Flash Memories | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Tae Whan | - |
dc.identifier.doi | 10.1109/JEDS.2021.3104843 | - |
dc.identifier.scopusid | 2-s2.0-85113238943 | - |
dc.identifier.wosid | 000688215400001 | - |
dc.identifier.bibliographicCitation | IEEE Journal of the Electron Devices Society, v.9, pp.774 - 777 | - |
dc.relation.isPartOf | IEEE Journal of the Electron Devices Society | - |
dc.citation.title | IEEE Journal of the Electron Devices Society | - |
dc.citation.volume | 9 | - |
dc.citation.startPage | 774 | - |
dc.citation.endPage | 777 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | GRAIN-BOUNDARY TRAPS | - |
dc.subject.keywordPlus | THICKNESS | - |
dc.subject.keywordPlus | SIZE | - |
dc.subject.keywordAuthor | Flash memories | - |
dc.subject.keywordAuthor | Logic gates | - |
dc.subject.keywordAuthor | Electron traps | - |
dc.subject.keywordAuthor | Threshold voltage | - |
dc.subject.keywordAuthor | Tools | - |
dc.subject.keywordAuthor | Programming | - |
dc.subject.keywordAuthor | Licenses | - |
dc.subject.keywordAuthor | 3-D NAND flash memories | - |
dc.subject.keywordAuthor | threshold voltage shift | - |
dc.subject.keywordAuthor | tapered channel | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9514533 | - |
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