Asymmetric Read Bias for Alleviating Cell-to-Cell Interference in 3D NAND Flash Memory
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Sim, Jae-Min | - |
dc.contributor.author | Song, Yun-Heub | - |
dc.date.accessioned | 2022-07-06T14:45:34Z | - |
dc.date.available | 2022-07-06T14:45:34Z | - |
dc.date.created | 2021-12-08 | - |
dc.date.issued | 2021-08 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/141233 | - |
dc.description.abstract | In this paper, we investigated cell-to-cell interference at read operation in scaling of 3D NAND flash memory and proposed a new read scheme to alleviating this issue. First, we confirmed the cell-to-cell interference according to each pattern. As a result, EEP pattern had more interference than the PEE pattern, because the PEE pattern was affected by the BL bias. It leads to conduction energy distortion of the selected cell, which was more severe at EEP pattern. Second, with scaling, conduction energy decreases, and it leads to more severe the interference issue. Finally, to solve this problem, asymmetric read bias was proposed, and it was confirmed that the pattern dependence of the cell-to-cell interference can be reduced. Compared with the conventional, the proposed read scheme reduces the difference in Vth shift value from 0.11V to 0.07V.Therefore, the proposed read scheme is expected to alleviate cell-to-cell interference in the scaling structure of the 3D NAND flash memory. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Asymmetric Read Bias for Alleviating Cell-to-Cell Interference in 3D NAND Flash Memory | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Song, Yun-Heub | - |
dc.identifier.doi | 10.1109/TENSYMP52854.2021.9550809 | - |
dc.identifier.scopusid | 2-s2.0-85117476859 | - |
dc.identifier.wosid | 000786502700006 | - |
dc.identifier.bibliographicCitation | TENSYMP 2021 - 2021 IEEE Region 10 Symposium, pp.1 - 4 | - |
dc.relation.isPartOf | TENSYMP 2021 - 2021 IEEE Region 10 Symposium | - |
dc.citation.title | TENSYMP 2021 - 2021 IEEE Region 10 Symposium | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 4 | - |
dc.type.rims | ART | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | Three-dimensional displays , Nonvolatile memory , Interference , Logic gates , Distortion , Silicon , Reliability | - |
dc.subject.keywordPlus | distortion , flash memories , interference suppression , NAND circuits , three-dimensional integrated circuits | - |
dc.subject.keywordAuthor | 3D NAND flash memory | - |
dc.subject.keywordAuthor | interference | - |
dc.subject.keywordAuthor | non-volatile memory (NVM) | - |
dc.subject.keywordAuthor | read operation | - |
dc.subject.keywordAuthor | scaling | - |
dc.identifier.url | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9550809 | - |
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