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Lumped Parameter Modeling based Power Loop Analysis Technique of Power Circuit Bo aid with Wide Conduction Aiea for WBG Semiconductors
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Cho, Min-Shin | - |
| dc.contributor.author | Kim, Rae Young | - |
| dc.date.accessioned | 2022-07-07T01:20:45Z | - |
| dc.date.available | 2022-07-07T01:20:45Z | - |
| dc.date.issued | 2021-01 | - |
| dc.identifier.issn | 1975-8359 | - |
| dc.identifier.issn | 2287-4364 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/142440 | - |
| dc.description.abstract | In this paper, we propose a power loop analysis method based on limped parameter modeling of power circuit board with wide current conduction area for WBG power semiconductors. The proposed analysis method is modeled with lumped parameter so that power loops having various current paths can be analyzed, so the analysis is simple, easy to apply, and has the advantage of enabling dynamic power loop analysis. The validity of the lumped parameter model was verified through LTSPICE and Q3D simulation results. | - |
| dc.format.extent | 10 | - |
| dc.language | 한국어 | - |
| dc.language.iso | KOR | - |
| dc.publisher | 대한전기학회 | - |
| dc.title | Lumped Parameter Modeling based Power Loop Analysis Technique of Power Circuit Bo aid with Wide Conduction Aiea for WBG Semiconductors | - |
| dc.title.alternative | WBG 전력 반도체를 위한 넓은 전류 도통 영역을 갖는 전력 회로 보드의 집중정수 모델링 기반 파워 루프 해석 기법 | - |
| dc.type | Article | - |
| dc.publisher.location | 대한민국 | - |
| dc.identifier.doi | 10.5370/KIEE.2021.70.1.079 | - |
| dc.identifier.scopusid | 2-s2.0-85102522145 | - |
| dc.identifier.bibliographicCitation | 전기학회논문지, v.70, no.1, pp 79 - 88 | - |
| dc.citation.title | 전기학회논문지 | - |
| dc.citation.volume | 70 | - |
| dc.citation.number | 1 | - |
| dc.citation.startPage | 79 | - |
| dc.citation.endPage | 88 | - |
| dc.type.docType | Article | - |
| dc.identifier.kciid | ART002673345 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.description.journalRegisteredClass | kci | - |
| dc.subject.keywordPlus | Electric network analysis | - |
| dc.subject.keywordPlus | Timing circuits | - |
| dc.subject.keywordPlus | Analysis method | - |
| dc.subject.keywordPlus | Current conduction | - |
| dc.subject.keywordPlus | Current paths | - |
| dc.subject.keywordPlus | Loop analysis technique | - |
| dc.subject.keywordPlus | Lumped parameter | - |
| dc.subject.keywordPlus | Lumped parameter modeling | - |
| dc.subject.keywordPlus | Parameter model | - |
| dc.subject.keywordPlus | Power semiconductors | - |
| dc.subject.keywordPlus | Lumped parameter networks | - |
| dc.subject.keywordAuthor | Analysis | - |
| dc.subject.keywordAuthor | Lumped parameter modeling | - |
| dc.subject.keywordAuthor | Power loop | - |
| dc.subject.keywordAuthor | Wbg semiconductors | - |
| dc.subject.keywordAuthor | Wide conduction area | - |
| dc.identifier.url | https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE10514353&language=ko_KR&hasTopBanner=true | - |
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Related Researcher
- Kim, Rae Young
- COLLEGE OF ENGINEERING (MAJOR IN ELECTRICAL ENGINEERING)