Speed Enhancement of WSi2 Nanocrystal Memory with Barrier-Engineered Si3N4/HfAlO Tunnel Layer
DC Field | Value | Language |
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dc.contributor.author | Lee, Dong Uk | - |
dc.contributor.author | Lee, Hyo Jun | - |
dc.contributor.author | Kim, Eun Kyu | - |
dc.contributor.author | You, Hee-Wook | - |
dc.contributor.author | Cho, Won-Ju | - |
dc.date.accessioned | 2022-07-07T13:55:11Z | - |
dc.date.available | 2022-07-07T13:55:11Z | - |
dc.date.created | 2021-05-12 | - |
dc.date.issued | 2012-06 | - |
dc.identifier.issn | 0021-4922 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/144760 | - |
dc.description.abstract | WSi2 nanocrystal nanofloating gate capacitors with multistacked Si3N4/HfAlO high-k tunnel layers were fabricated and their electrical properties were characterized. The thicknesses of the Si3N4 and HfAlO tunnel layers were 1.5 and 3 nm, respectively. The asymmetrical Si3N4/HfAlO tunnel layer was modulated to enhance the tunneling efficiency to improve program and erase speeds. The flat-band voltage shift of the WSi2 nanofloating gate capacitor was about 7.2 V after applied voltages swept were from -10 to 10 V and from 10 to -10 V. Then, the program/erase speeds and the memory window under programming and erasing at +/- 7 V were 300 mu s and 1 V, respectively. As demonstrated in the results, the WSi2 nanocrystal memory with barrier-engineered Si3N4/HfAlO layers could be applied to enhance the program and erase speeds at low operating voltages for nanocrystal nonvolatile memory application. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IOP PUBLISHING LTD | - |
dc.title | Speed Enhancement of WSi2 Nanocrystal Memory with Barrier-Engineered Si3N4/HfAlO Tunnel Layer | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Eun Kyu | - |
dc.identifier.doi | 10.1143/JJAP.51.06FE13 | - |
dc.identifier.scopusid | 2-s2.0-84863324066 | - |
dc.identifier.wosid | 000306189800060 | - |
dc.identifier.bibliographicCitation | JAPANESE JOURNAL OF APPLIED PHYSICS, v.51, no.6, pp.1 - 5 | - |
dc.relation.isPartOf | JAPANESE JOURNAL OF APPLIED PHYSICS | - |
dc.citation.title | JAPANESE JOURNAL OF APPLIED PHYSICS | - |
dc.citation.volume | 51 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 5 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | FLOATING-GATE MEMORY | - |
dc.subject.keywordPlus | FABRICATION | - |
dc.subject.keywordPlus | NANOPARTICLES | - |
dc.identifier.url | https://iopscience.iop.org/article/10.1143/JJAP.51.06FE13 | - |
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