Automated Neural Network Accelerator Generation Framework for Multiple Neural Network Applications
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Inho | - |
dc.contributor.author | Hong, Seongmin | - |
dc.contributor.author | Ryu, Giha | - |
dc.contributor.author | Park, Yongjun | - |
dc.date.accessioned | 2022-07-09T06:40:08Z | - |
dc.date.available | 2022-07-09T06:40:08Z | - |
dc.date.created | 2021-05-11 | - |
dc.date.issued | 2019-10 | - |
dc.identifier.issn | 2159-3442 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/147092 | - |
dc.description.abstract | Neural networks are widely used in various applications, but general neural network accelerators support only one application at a time. Therefore, information for each application, such as synaptic weights and bias data, must be loaded quickly to use multiple neural network applications. Field-programmable gate array (FPGA)-based implementation has huge performance overhead owing to low data transmission bandwidth. In order to solve this problem, this paper presents an automated FPGA-based multi-neural network accelerator generation framework that can quickly support several applications by storing neural network application data in an on-chip memory inside the FPGA. To do this, we first design a shared custom hardware accelerator that can support rapid changes in multiple target neural network applications. Then, we introduce an automated multi-neural network accelerator generation framework that performs training, weight quantization, and neural accelerator synthesis. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Automated Neural Network Accelerator Generation Framework for Multiple Neural Network Applications | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Yongjun | - |
dc.identifier.doi | 10.1109/TENCON.2018.8650190 | - |
dc.identifier.scopusid | 2-s2.0-85063208887 | - |
dc.identifier.wosid | 000465799100436 | - |
dc.identifier.bibliographicCitation | IEEE Region 10 Annual International Conference, Proceedings/TENCON, v.2018-October, pp.2287 - 2290 | - |
dc.relation.isPartOf | IEEE Region 10 Annual International Conference, Proceedings/TENCON | - |
dc.citation.title | IEEE Region 10 Annual International Conference, Proceedings/TENCON | - |
dc.citation.volume | 2018-October | - |
dc.citation.startPage | 2287 | - |
dc.citation.endPage | 2290 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering | - |
dc.relation.journalWebOfScienceCategory | Electrical & Electronic | - |
dc.subject.keywordPlus | Automation | - |
dc.subject.keywordPlus | Field programmable gate arrays (FPGA) | - |
dc.subject.keywordPlus | Neural networks | - |
dc.subject.keywordPlus | Particle accelerators | - |
dc.subject.keywordPlus | Custom hardwares | - |
dc.subject.keywordPlus | First designs | - |
dc.subject.keywordPlus | Multi-neural networks | - |
dc.subject.keywordPlus | Multiple neural networks | - |
dc.subject.keywordPlus | Multiple targets | - |
dc.subject.keywordPlus | Neural network application | - |
dc.subject.keywordPlus | On chip memory | - |
dc.subject.keywordPlus | Synaptic weight | - |
dc.subject.keywordPlus | Acceleration | - |
dc.subject.keywordAuthor | accelerator | - |
dc.subject.keywordAuthor | FPGA | - |
dc.subject.keywordAuthor | neural network | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/8650190 | - |
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