Core-level DVFS for Spatial Multitasking GPUs
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cha, Jehee | - |
dc.contributor.author | Kim, Jiho | - |
dc.contributor.author | Park, Yongjun | - |
dc.date.accessioned | 2022-07-09T06:40:12Z | - |
dc.date.available | 2022-07-09T06:40:12Z | - |
dc.date.created | 2021-05-11 | - |
dc.date.issued | 2019-10 | - |
dc.identifier.issn | 2159-3442 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/147093 | - |
dc.description.abstract | DVFS (Dynamic voltage frequency scaling) is one of the most widely used power management technologies employed to improve the performance or minimize the power consumption by controlling voltages and frequencies in real time. When applying device-level DVFS in graphics processing units (GPUs) that support spatial multitasking, it is difficult to determine the optimal DVFS status when multiple running kernels have different characteristics. To solve the problem, we created a GPU simulator that can operate at different streaming multiprocessor frequencies according to the characteristics of the assigned kernel and compared it with a single-clock-based spatial multitasking GPU simulator. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Core-level DVFS for Spatial Multitasking GPUs | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Yongjun | - |
dc.identifier.doi | 10.1109/TENCON.2018.8650072 | - |
dc.identifier.scopusid | 2-s2.0-85063236818 | - |
dc.identifier.wosid | 000465799100292 | - |
dc.identifier.bibliographicCitation | IEEE Region 10 Annual International Conference, Proceedings/TENCON, v.2018-October, pp.1525 - 1528 | - |
dc.relation.isPartOf | IEEE Region 10 Annual International Conference, Proceedings/TENCON | - |
dc.citation.title | IEEE Region 10 Annual International Conference, Proceedings/TENCON | - |
dc.citation.volume | 2018-October | - |
dc.citation.startPage | 1525 | - |
dc.citation.endPage | 1528 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | Computer graphics | - |
dc.subject.keywordPlus | Dynamic frequency scaling | - |
dc.subject.keywordPlus | Multitasking | - |
dc.subject.keywordPlus | Program processors | - |
dc.subject.keywordPlus | Voltage scaling | - |
dc.subject.keywordPlus | DVFS | - |
dc.subject.keywordPlus | Dynamic voltage frequency scaling | - |
dc.subject.keywordPlus | Gpu simulators | - |
dc.subject.keywordPlus | Power management technology | - |
dc.subject.keywordPlus | Real time | - |
dc.subject.keywordPlus | Single clock | - |
dc.subject.keywordPlus | Streaming multiprocessors | - |
dc.subject.keywordPlus | Graphics processing unit | - |
dc.subject.keywordAuthor | DVFS | - |
dc.subject.keywordAuthor | GPU | - |
dc.subject.keywordAuthor | Multitasking | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/8650072 | - |
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