GATE: A generalized dataflow-level approximation tuning engine for data parallel architectures
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kang, Seokwon . | - |
dc.contributor.author | Yu, Yongseung | - |
dc.contributor.author | Kim, Jiho | - |
dc.contributor.author | Park, Yongjun | - |
dc.date.accessioned | 2022-07-09T14:01:59Z | - |
dc.date.available | 2022-07-09T14:01:59Z | - |
dc.date.created | 2021-05-13 | - |
dc.date.issued | 2019-06 | - |
dc.identifier.issn | 0738-100X | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/147627 | - |
dc.description.abstract | Although approximate computing is widely used, it requires substantial programming effort to find appropriate approximation patterns among multiple pre-defined patterns to achieve a high performance. Therefore, we propose an automatic approximation framework called GATE to uncover hidden opportunities from any data-parallel program regardless of the code pattern or application characteristics using two compiler techniques, namely subgraph-level approximation (SGLA) and approximate thread merge(ATM). GATE also features conservative/aggressive tuning and dynamic calibration to maximize the performance while maintaining the TOQ level during runtime. Our framework achieves an average performance gain of 2.54x over the baseline with minimum accuracy loss. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | GATE: A generalized dataflow-level approximation tuning engine for data parallel architectures | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Yongjun | - |
dc.identifier.doi | 10.1145/3316781.3317833 | - |
dc.identifier.scopusid | 2-s2.0-85067808752 | - |
dc.identifier.wosid | 000482058200024 | - |
dc.identifier.bibliographicCitation | Proceedings - Design Automation Conference, pp.1 - 6 | - |
dc.relation.isPartOf | Proceedings - Design Automation Conference | - |
dc.citation.title | Proceedings - Design Automation Conference | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 6 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Software Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Theory & Methods | - |
dc.subject.keywordPlus | Application programs | - |
dc.subject.keywordPlus | Computer aided design | - |
dc.subject.keywordPlus | Program compilers | - |
dc.subject.keywordPlus | Accuracy loss | - |
dc.subject.keywordPlus | Code-patterns | - |
dc.subject.keywordPlus | Compiler techniques | - |
dc.subject.keywordPlus | Data parallel | - |
dc.subject.keywordPlus | Data-parallel architectures | - |
dc.subject.keywordPlus | Dynamic calibration | - |
dc.subject.keywordPlus | OR applications | - |
dc.subject.keywordPlus | Performance Gain | - |
dc.subject.keywordPlus | Parallel architectures | - |
dc.identifier.url | https://dl.acm.org/doi/10.1145/3316781.3317833 | - |
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