Adaptive Cooperation of Prefetching and Warp Scheduling on GPUs
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Oh, Yunho | - |
dc.contributor.author | Kim, Keunsoo | - |
dc.contributor.author | Yoon, Myung Kuk | - |
dc.contributor.author | Park, Jong Hyun | - |
dc.contributor.author | Park, Yongjun | - |
dc.contributor.author | Annavaram, Murali | - |
dc.contributor.author | Ro, Won Woo | - |
dc.date.accessioned | 2022-07-09T19:25:25Z | - |
dc.date.available | 2022-07-09T19:25:25Z | - |
dc.date.created | 2021-05-12 | - |
dc.date.issued | 2019-04 | - |
dc.identifier.issn | 0018-9340 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/148018 | - |
dc.description.abstract | This paper proposes a new architecture, called Adaptive PREfetching and Scheduling (APRES), which improves cache efficiency of GPUs. APRES relies on the observation that GPU loads tend to have either high locality or strided access patterns across warps. APRES schedules warps so that as many cache hits are generated as possible before the generation of any cache miss. Without directly predicting future cache hits/misses for each warp, APRES creates a warp group that will execute the same static load shortly and prioritizes the grouped warps. If the first executed warp in the group hits the cache, grouped warps are likely to access the same cache lines. Unless, APRES considers the load as a strided type and generates prefetch requests for the grouped warps. In addition, APRES includes a new dynamic L1 prefetch and data cache partitioning to reduce contentions between demand-fetched and prefetched lines. In our evaluation, APRES achieves 27.8 percent performance improvement. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE COMPUTER SOC | - |
dc.title | Adaptive Cooperation of Prefetching and Warp Scheduling on GPUs | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Yongjun | - |
dc.identifier.doi | 10.1109/TC.2018.2878671 | - |
dc.identifier.scopusid | 2-s2.0-85055870610 | - |
dc.identifier.wosid | 000461236900011 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON COMPUTERS, v.68, no.4, pp.609 - 616 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON COMPUTERS | - |
dc.citation.title | IEEE TRANSACTIONS ON COMPUTERS | - |
dc.citation.volume | 68 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 609 | - |
dc.citation.endPage | 616 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | Cache memory | - |
dc.subject.keywordPlus | Computer architecture | - |
dc.subject.keywordPlus | Computer graphics | - |
dc.subject.keywordPlus | Electronic mail | - |
dc.subject.keywordPlus | Program processors | - |
dc.subject.keywordPlus | Scheduling | - |
dc.subject.keywordPlus | cache | - |
dc.subject.keywordPlus | Data pre-fetching | - |
dc.subject.keywordPlus | performance | - |
dc.subject.keywordPlus | Prefetching | - |
dc.subject.keywordPlus | Superluminescent diode | - |
dc.subject.keywordPlus | Warp scheduling | - |
dc.subject.keywordPlus | Graphics processing unit | - |
dc.subject.keywordAuthor | GPU | - |
dc.subject.keywordAuthor | cache | - |
dc.subject.keywordAuthor | warp scheduling | - |
dc.subject.keywordAuthor | data prefetching | - |
dc.subject.keywordAuthor | performance | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/8515055 | - |
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