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Adaptive Cooperation of Prefetching and Warp Scheduling on GPUs

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dc.contributor.authorOh, Yunho-
dc.contributor.authorKim, Keunsoo-
dc.contributor.authorYoon, Myung Kuk-
dc.contributor.authorPark, Jong Hyun-
dc.contributor.authorPark, Yongjun-
dc.contributor.authorAnnavaram, Murali-
dc.contributor.authorRo, Won Woo-
dc.date.accessioned2022-07-09T19:25:25Z-
dc.date.available2022-07-09T19:25:25Z-
dc.date.created2021-05-12-
dc.date.issued2019-04-
dc.identifier.issn0018-9340-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/148018-
dc.description.abstractThis paper proposes a new architecture, called Adaptive PREfetching and Scheduling (APRES), which improves cache efficiency of GPUs. APRES relies on the observation that GPU loads tend to have either high locality or strided access patterns across warps. APRES schedules warps so that as many cache hits are generated as possible before the generation of any cache miss. Without directly predicting future cache hits/misses for each warp, APRES creates a warp group that will execute the same static load shortly and prioritizes the grouped warps. If the first executed warp in the group hits the cache, grouped warps are likely to access the same cache lines. Unless, APRES considers the load as a strided type and generates prefetch requests for the grouped warps. In addition, APRES includes a new dynamic L1 prefetch and data cache partitioning to reduce contentions between demand-fetched and prefetched lines. In our evaluation, APRES achieves 27.8 percent performance improvement.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE COMPUTER SOC-
dc.titleAdaptive Cooperation of Prefetching and Warp Scheduling on GPUs-
dc.typeArticle-
dc.contributor.affiliatedAuthorPark, Yongjun-
dc.identifier.doi10.1109/TC.2018.2878671-
dc.identifier.scopusid2-s2.0-85055870610-
dc.identifier.wosid000461236900011-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON COMPUTERS, v.68, no.4, pp.609 - 616-
dc.relation.isPartOfIEEE TRANSACTIONS ON COMPUTERS-
dc.citation.titleIEEE TRANSACTIONS ON COMPUTERS-
dc.citation.volume68-
dc.citation.number4-
dc.citation.startPage609-
dc.citation.endPage616-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusCache memory-
dc.subject.keywordPlusComputer architecture-
dc.subject.keywordPlusComputer graphics-
dc.subject.keywordPlusElectronic mail-
dc.subject.keywordPlusProgram processors-
dc.subject.keywordPlusScheduling-
dc.subject.keywordPluscache-
dc.subject.keywordPlusData pre-fetching-
dc.subject.keywordPlusperformance-
dc.subject.keywordPlusPrefetching-
dc.subject.keywordPlusSuperluminescent diode-
dc.subject.keywordPlusWarp scheduling-
dc.subject.keywordPlusGraphics processing unit-
dc.subject.keywordAuthorGPU-
dc.subject.keywordAuthorcache-
dc.subject.keywordAuthorwarp scheduling-
dc.subject.keywordAuthordata prefetching-
dc.subject.keywordAuthorperformance-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8515055-
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