Design of Low-Power Voltage Scalable Arithmetic Units with Perfect Timing Error Cancelation

Abstract

Many of the existing supply voltage overscaling (VOS) techniques allow an increase in the critical path delay, resulting in the reduction in the throughput rate. On the contrary, the VOS techniques without affecting on the throughput rate induce loss of the system performance by timing errors. In this paper, we propose a perfect timing error cancelation (PTEC) system which not only retains the throughput rate, but also perfectly recovers the system performance. In the arithmetic units whose output bits are sequentially computed, it is observed that timing violations due to VOS occur at some designated highest order output bits, resulting in the large error on the output value. By exploiting this property, a novel timing error cancelation technique is presented by modeling the timing error signal and deriving the condition for the perfect recovery from the impaired signal. The proposed PTEC system is verified with the design example of a 1616 unsigned carry-save multiplier. From simulation results, it is found that the proposed PTEC system with 200 mV overscaling offers 38% power reduction with maintaining the throughput rate as well as the system functionality compared to the conventional design with the nominal supply voltage (=1 V).