Optimal Checkpoint Selection with Dual-Modular Redundancy Hardening
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kang, Shin-Haeng | - |
dc.contributor.author | Park, Hae-woo | - |
dc.contributor.author | Kim, Sungchan | - |
dc.contributor.author | Oh, Hyunok | - |
dc.contributor.author | Ha, Soonhoi | - |
dc.date.accessioned | 2022-07-15T22:02:35Z | - |
dc.date.available | 2022-07-15T22:02:35Z | - |
dc.date.created | 2021-05-12 | - |
dc.date.issued | 2015-07 | - |
dc.identifier.issn | 0018-9340 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/156842 | - |
dc.description.abstract | With the continuous scaling of semiconductor technology, failure rate is increasing significantly so that reliability becomes an important issue in multiprocessor system-on-chip (MPSoC) design. We propose an optimal checkpoint selection with task duplication hardening to tolerate transient faults. A target application is specified in a task graph, and the schedule/checkpoint placements are determined at design time. The proposed optimal algorithm minimizes the checkpoint overhead with a latency constraint. Experimental results show that the proposed algorithm effectively reduces the minimum end-to-end latency to perform a fault-tolerant schedule. In addition, the proposed algorithm dramatically decreases the checkpointing overhead on uniprocessor and multiprocessor systems compared with a greedy approach and an equidistant algorithm. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE COMPUTER SOC | - |
dc.title | Optimal Checkpoint Selection with Dual-Modular Redundancy Hardening | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Oh, Hyunok | - |
dc.identifier.doi | 10.1109/TC.2014.2349492 | - |
dc.identifier.scopusid | 2-s2.0-84933074039 | - |
dc.identifier.wosid | 000355989900018 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON COMPUTERS, v.64, no.7, pp.2036 - 2048 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON COMPUTERS | - |
dc.citation.title | IEEE TRANSACTIONS ON COMPUTERS | - |
dc.citation.volume | 64 | - |
dc.citation.number | 7 | - |
dc.citation.startPage | 2036 | - |
dc.citation.endPage | 2048 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | SOFTWARE | - |
dc.subject.keywordPlus | PROCESSORS | - |
dc.subject.keywordPlus | RELIABILITY | - |
dc.subject.keywordPlus | CHECKING | - |
dc.subject.keywordAuthor | Checkpoint | - |
dc.subject.keywordAuthor | task graph | - |
dc.subject.keywordAuthor | multiprocessor | - |
dc.subject.keywordAuthor | reliability | - |
dc.subject.keywordAuthor | optimal algorithm | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/6880324 | - |
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