Successive Elimination Algorithm for Constrained One-bit Transform Based Motion Estimation Using the Bonferroni Inequality
DC Field | Value | Language |
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dc.contributor.author | Choi, Changryoul | - |
dc.contributor.author | Jeong, Jechang | - |
dc.date.accessioned | 2022-07-16T02:39:33Z | - |
dc.date.available | 2022-07-16T02:39:33Z | - |
dc.date.created | 2021-05-12 | - |
dc.date.issued | 2014-10 | - |
dc.identifier.issn | 1070-9908 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/158962 | - |
dc.description.abstract | The constrained one-bit transform (C1BT) was proposed to increase the motion estimation (ME) accuracy of the previous one-bit transform (1BT) especially for small motion blocks. Although making another bit-plane is very simple and efficient, its performance is even better than that of the two-bit transform (2BT) based ME. However, unlike the 1BT-based ME and the 2BT-based ME, the successive elimination algorithm (SEA) based on the triangle inequality for C1BT-based ME cannot be derived because C1BT matching error criterion does not satisfy the typical measure conditions. In this letter, a fast full-search block matching algorithm for C1BT-based ME is developed. The proposed algorithm evaluates lower bounds for constrained one-bit matching criterion based on the Bonferroni inequality to eliminate the impossible candidates faster and save computations substantially. Experimental results show that while the ME accuracy of the proposed algorithm is the same as that of the full search C1BT, the proposed algorithm reduces computational complexity significantly. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Successive Elimination Algorithm for Constrained One-bit Transform Based Motion Estimation Using the Bonferroni Inequality | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Jeong, Jechang | - |
dc.identifier.doi | 10.1109/LSP.2014.2328992 | - |
dc.identifier.scopusid | 2-s2.0-84903782839 | - |
dc.identifier.wosid | 000339166600002 | - |
dc.identifier.bibliographicCitation | IEEE SIGNAL PROCESSING LETTERS, v.21, no.10, pp.1260 - 1264 | - |
dc.relation.isPartOf | IEEE SIGNAL PROCESSING LETTERS | - |
dc.citation.title | IEEE SIGNAL PROCESSING LETTERS | - |
dc.citation.volume | 21 | - |
dc.citation.number | 10 | - |
dc.citation.startPage | 1260 | - |
dc.citation.endPage | 1264 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | 2-BIT TRANSFORM | - |
dc.subject.keywordPlus | HARDWARE ARCHITECTURE | - |
dc.subject.keywordAuthor | Bit-plane matching | - |
dc.subject.keywordAuthor | motion estimation | - |
dc.subject.keywordAuthor | successive elimination algorithm | - |
dc.subject.keywordAuthor | video coding | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/6825878 | - |
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