On-state darin current modeling for grain and grain boundary effect of the polysilicon materials at various temperatures

Abstract

We present analytical on-state drain current model of 2-dimensional (2D) planar-type poly-Silicon TFT devices. The effect of grain and grain boundary on the carrier transport of 2D poly-Silicon devices has been studied by simulation (matlab) tool. Especially, we considered physical parameters such as grain length (L<inf>g</inf>), grain boundary length (L<inf>gb</inf>) and grain boundary trap density (N<inf>GB</inf>) in order to analyze cell performance of the poly-Silicon materials at various temperature. Thus, we simulated the temperature dependence of the on-state drain current within a wide temperature range from 248 K (-25 °C) to 348 K (75 °C). From these results, we confirmed that grain length and grain boundary trap density significantly effects on-state drain current in poly-Silicon materials.