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Design and implementation of GPU-based turbo decoder with a minimal latency

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dc.contributor.authorAhn, Heungseop-
dc.contributor.authorJin, Yong-
dc.contributor.authorHan, Sangwook-
dc.contributor.authorChoi, Seungwon-
dc.contributor.authorAhn, Sungsoo-
dc.date.accessioned2022-07-16T04:27:44Z-
dc.date.available2022-07-16T04:27:44Z-
dc.date.created2021-05-13-
dc.date.issued2014-06-
dc.identifier.issn0000-0000-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/159797-
dc.description.abstractDecoding latency of the turbo decoder has been a serious problem in real-time processing of communication systems. This paper presents a novel procedure of reducing the latency of the turbo decoder which has been implemented with GPU (Graphic Processing Unit). The main contribution of this paper is to present an efficient procedure of reducing the latency of GPU-based turbo decoder through an efficient parallel processing of maximum a posteriori (MAP). Through experimental tests, we have verified that the proposed turbo decoder reduces the latency from 34,767μs to 273μs per iteration.-
dc.language영어-
dc.language.isoen-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleDesign and implementation of GPU-based turbo decoder with a minimal latency-
dc.typeArticle-
dc.contributor.affiliatedAuthorChoi, Seungwon-
dc.identifier.doi10.1109/ISCE.2014.6884510-
dc.identifier.scopusid2-s2.0-84907401326-
dc.identifier.bibliographicCitationProceedings of the International Symposium on Consumer Electronics, ISCE, pp.1 - 2-
dc.relation.isPartOfProceedings of the International Symposium on Consumer Electronics, ISCE-
dc.citation.titleProceedings of the International Symposium on Consumer Electronics, ISCE-
dc.citation.startPage1-
dc.citation.endPage2-
dc.type.rimsART-
dc.type.docTypeConference Paper-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscopus-
dc.subject.keywordPlusElectronics engineering-
dc.subject.keywordPlusElectronics industry-
dc.subject.keywordPlusCUDA-
dc.subject.keywordPlusDesign and implementations-
dc.subject.keywordPlusGPU-
dc.subject.keywordPlusGraphic processing units-
dc.subject.keywordPlusMAP decoder-
dc.subject.keywordPlusMaximum a posteriori-
dc.subject.keywordPlusParallel processing-
dc.subject.keywordPlusTurbo decoders-
dc.subject.keywordPlusConsumer electronics-
dc.subject.keywordAuthorCUDA-
dc.subject.keywordAuthorGPU-
dc.subject.keywordAuthorparallel MAP decoder-
dc.subject.keywordAuthorTurbo decoder-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/6884510-
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