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An energy aware buffer mapping technique on hybrid STT-MRAM memories with multiple retention time for stream applications

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dc.contributor.authorChoi, Kwangil-
dc.contributor.authorOh, Hyunok-
dc.date.accessioned2022-07-16T08:27:01Z-
dc.date.available2022-07-16T08:27:01Z-
dc.date.created2021-05-12-
dc.date.issued2013-09-
dc.identifier.issn0929-5585-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/162025-
dc.description.abstractSTT-MRAM has been recently researched to replace DRAM in order to reduce the cell size and save the leakage power consumption. Although the read operation in STT-MRAM is acceptable in terms of performance and energy consumption, the write operation discourages the adoption of the STT-MRAM as main memory. A promising approach to overcome the poor write operation is to reduce the planar cell size which decreases the retention time, the write latency and the write energy consumption since the change of the cell size requires no additional manufacturing process. However, since refresh is required in the reduced retention time memory just like DRAM, the leakage energy consumption may increase compared with a traditional STT-MRAM with long retention time. This paper solves the buffer mapping problem onto a system with multiple retention time memories for a stream application to minimize the energy consumption. Experimental results show that a system with two or three different retention time STT-MRAMs reduces 45-75 % of write energy consumption compared with a single long retention time STT-MRAM.-
dc.language영어-
dc.language.isoen-
dc.publisherSPRINGER-
dc.titleAn energy aware buffer mapping technique on hybrid STT-MRAM memories with multiple retention time for stream applications-
dc.typeArticle-
dc.contributor.affiliatedAuthorOh, Hyunok-
dc.identifier.doi10.1007/s10617-014-9147-4-
dc.identifier.scopusid2-s2.0-84939461984-
dc.identifier.wosid000209315300010-
dc.identifier.bibliographicCitationDESIGN AUTOMATION FOR EMBEDDED SYSTEMS, v.17, no.3-4, pp.693 - 710-
dc.relation.isPartOfDESIGN AUTOMATION FOR EMBEDDED SYSTEMS-
dc.citation.titleDESIGN AUTOMATION FOR EMBEDDED SYSTEMS-
dc.citation.volume17-
dc.citation.number3-4-
dc.citation.startPage693-
dc.citation.endPage710-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryComputer Science, Software Engineering-
dc.subject.keywordPlusCACHE-
dc.subject.keywordPlusData flow analysis-
dc.subject.keywordPlusDynamic random access storage-
dc.subject.keywordPlusEnergy utilization-
dc.subject.keywordPlusMagnetic recording-
dc.subject.keywordPlusMagnetic storage-
dc.subject.keywordAuthorSTT-MRAM-
dc.subject.keywordAuthorRetention time-
dc.subject.keywordAuthorSynchronous dataflow graph-
dc.subject.keywordAuthorEnergy minimization-
dc.subject.keywordAuthorBuffer mapping-
dc.identifier.urlhttps://link.springer.com/article/10.1007/s10617-014-9147-4-
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