Degradation Mechanisms of the Program Characteristics of 10 nm NAND Flash Memories Due to Cell-to-Cell Interference

Abstract

The device characteristics of NAND flash memories with gate sizes from 14 to 32 nm were investigated by using a full three-dimensional technology computer-aided design simulator. Simulation results showed that the threshold voltage and the depletion regions of the floating gate (FG) of the 10-nm NAND flash memories increased with decreasing cell size. The electrical potential of the inter-poly-dielectric (IPD) surface and the tunneling layer surface decreased with increasing depletion region of the FG. The program characteristics of the 10-nm NAND flash memories decreased with decreasing electric potential on the IPD surface and the tunneling oxide surface. The electric field between the floating gate of the target cell and that of the neighboring cell increased with decreasing gate size due to a decrease in the distance between the two neighboring cells. The degradation mechanisms for the program characteristics of 10-nm NAND flash memories were clarified by changing the threshold voltage and the voltage shift.