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Construction of High-Rate Regular Quasi-Cyclic LDPC Codes Based on Cyclic Difference Families

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dc.contributor.authorPark, Hosung-
dc.contributor.authorHong, Seokbeom-
dc.contributor.authorNo, Jong-Seon-
dc.contributor.authorShin, Dong-Joon-
dc.date.accessioned2022-07-16T08:43:30Z-
dc.date.available2022-07-16T08:43:30Z-
dc.date.created2021-05-12-
dc.date.issued2013-08-
dc.identifier.issn0090-6778-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/162231-
dc.description.abstractFor a high-rate case, it is difficult to randomly construct good low-density parity-check (LDPC) codes of short and moderate lengths because their Tanner graphs are prone to have short cycles. Also, the existing high-rate quasi-cyclic (QC) LDPC codes can be constructed only for very restricted code parameters. In this paper, based on special classes of cyclic difference families, we propose a new construction method of high-rate regular QC LDPC codes having parity-check matrices consisting of a single row of circulants with column-weight 3 or 4. The proposed QC LDPC codes can be constructed for various code rates and lengths including the minimum achievable length for given column-weight and design rate under girth 6. It is observed that the parity-check matrices of the proposed QC LDPC codes have full rank for column-weight 3 and just one redundant row for column-weight 4. It is shown that the error correcting performance of the proposed QC LDPC codes of short and moderate lengths is almost the same as that of the existing ones through numerical analysis.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleConstruction of High-Rate Regular Quasi-Cyclic LDPC Codes Based on Cyclic Difference Families-
dc.typeArticle-
dc.contributor.affiliatedAuthorShin, Dong-Joon-
dc.identifier.doi10.1109/TCOMM.2013.070213.120879-
dc.identifier.scopusid2-s2.0-84883239360-
dc.identifier.wosid000323647500004-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON COMMUNICATIONS, v.61, no.8, pp.3108 - 3113-
dc.relation.isPartOfIEEE TRANSACTIONS ON COMMUNICATIONS-
dc.citation.titleIEEE TRANSACTIONS ON COMMUNICATIONS-
dc.citation.volume61-
dc.citation.number8-
dc.citation.startPage3108-
dc.citation.endPage3113-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.isOpenAccessY-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaTelecommunications-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryTelecommunications-
dc.subject.keywordPlusPARITY-CHECK CODES-
dc.subject.keywordPlusGEOMETRIES-
dc.subject.keywordPlusMATRICES-
dc.subject.keywordAuthorCode length-
dc.subject.keywordAuthorcode rate-
dc.subject.keywordAuthorcyclic difference families (CDFs)-
dc.subject.keywordAuthorgirth-
dc.subject.keywordAuthorquasi-cyclic (QC) low-density parity-check (LDPC) codes-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/6560065-
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