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Implementation of MCP-based WiMAX receiver test-bed for reconfigurable SDR handset
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, Hyungsub | - |
| dc.contributor.author | Kim, Hantaek | - |
| dc.contributor.author | Ahn, Chiyoung | - |
| dc.contributor.author | Kim, June | - |
| dc.contributor.author | Ahn, Sungsoo | - |
| dc.contributor.author | Choi, Seung won | - |
| dc.date.accessioned | 2022-07-16T11:26:16Z | - |
| dc.date.available | 2022-07-16T11:26:16Z | - |
| dc.date.created | 2021-05-13 | - |
| dc.date.issued | 2013-01 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/163561 | - |
| dc.description.abstract | This paper presents an implementation of MCP(Mobile Computing Platform)-based SDR(Software Defined Radio) handset platform, of which the main objective is to verify the feasibility and performance of baseband interface of reconfigurable SDR handset that is being standardized in ETSI(European Telecommunications Standards Institute) RRS(Reconfigurable Radio Systems). SDR platform in general requires a lot of arithmetic signal processing procedures, which brings about several restrictions in implementing the SDR platform using MCP because MCP consists of mobile processor only. In order to resolve those restrictions, we have adopted OMAP(Open Multimedia Application Platform) SoC(System on Chip) as a software modem platform, which itself is a mobile processor consisting of ARM(Advanced RISC Machine) and DSP(Digital Signal Processor) that are capable of high-speed digital signal processing. We propose an MCP-based SDR platform architecture that fully supports on-going ETSI RRS standard using OMAP SoC and FPGA(Field Programmable Gate Array)s. The proposed software architecture consists of AP(Application Processor) and RP(Radio Processor). ARM processor makes the AP providing the functionality of mobile OS(Operating System) driver and flexible control of reconfiguration of software modem, while FPGAs and DSP make RP providing the functionality of digital signal processing in PHY(Physical) layer. In order to verify the proposed architecture, WiMAX waveform has been selected for the proposed receiver test-bed. FPGA has been adopted for implementing Viterbi decoder because it requires the largest amount of computational load among all the PHY layer parts of implemented test-bed, while the other PHY layer parts (FFT(Fast Fourier Transform), channel estimation, soft decision, etc.) have been implemented on DSP. Performance of the implemented test-bed is shown in terms of software modem run-time, which guarantees that the baseband signal processing in accordance with the ETSI RRS standard can fully be supported by the proposed MCP-based platform test-bed in real-time. | - |
| dc.language | 영어 | - |
| dc.language.iso | en | - |
| dc.publisher | Wireless Innovation Forum | - |
| dc.title | Implementation of MCP-based WiMAX receiver test-bed for reconfigurable SDR handset | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Choi, Seung won | - |
| dc.identifier.bibliographicCitation | SDR-WinnComm 2013, pp.1 - 6 | - |
| dc.relation.isPartOf | SDR-WinnComm 2013 | - |
| dc.citation.title | SDR-WinnComm 2013 | - |
| dc.citation.startPage | 1 | - |
| dc.citation.endPage | 6 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Proceeding | - |
| dc.description.journalClass | 1 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | other | - |
| dc.identifier.url | https://www.wirelessinnovation.org/sdr-winncomm-2013 | - |
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