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Asymptotically Optimal Merging on ManyCore GPUs

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dc.contributor.authorKutzner, Arne-
dc.contributor.authorKim, Pok-Son-
dc.contributor.authorPark, Won-Kwang-
dc.date.accessioned2022-07-16T12:33:53Z-
dc.date.available2022-07-16T12:33:53Z-
dc.date.created2021-05-12-
dc.date.issued2012-12-
dc.identifier.issn1745-1361-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/164074-
dc.description.abstractWe propose a family of algorithms for efficiently merging on contemporary GPUs, so that each algorithm requires O(m log(n/m + 1)) element comparisons, where m and n are the sizes of the input sequences with m <= n. According to the lower bounds for merging all proposed algorithms are asymptotically optimal regarding the number of necessary comparisons. First we introduce a parallely structured algorithm that splits a merging problem of size 2(l) into 2(i) subproblems of size 2(l-i), for some arbitrary i with (0 <= i <= l). This algorithm represents a merger for i = 1 but it is rather inefficient in this case. The efficiency is boosted by moving to a two stage approach where the splitting process stops at some predetermined level and transfers control to several parallely operating block-mergers. We formally prove the asymptotic optimality of the splitting process and show that for symmetrically sized inputs our approach delivers up to 4 times faster runtimes than the thrust: :merge function that is part of the Thrust library. For assessing the value of our merging technique in the context of sorting we construct and evaluate a MergeSort on top of it. In the context of our benchmarking the resulting MergeSort clearly outperforms the MergeSort implementation provided by the Thrust library as well as Cederman's GPU optimized variant of QuickSort.-
dc.language영어-
dc.language.isoen-
dc.publisherIEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG-
dc.titleAsymptotically Optimal Merging on ManyCore GPUs-
dc.typeArticle-
dc.contributor.affiliatedAuthorKutzner, Arne-
dc.identifier.doi10.1587/transinf.E95.D.2769-
dc.identifier.scopusid2-s2.0-84870673096-
dc.identifier.wosid000313146300004-
dc.identifier.bibliographicCitationIEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E95D, no.12, pp.2769 - 2777-
dc.relation.isPartOfIEICE TRANSACTIONS ON INFORMATION AND SYSTEMS-
dc.citation.titleIEICE TRANSACTIONS ON INFORMATION AND SYSTEMS-
dc.citation.volumeE95D-
dc.citation.number12-
dc.citation.startPage2769-
dc.citation.endPage2777-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalWebOfScienceCategoryComputer Science, Information Systems-
dc.relation.journalWebOfScienceCategoryComputer Science, Software Engineering-
dc.subject.keywordPlusPARALLEL-
dc.subject.keywordPlusGRAPHICS-
dc.subject.keywordAuthorparallel algorithms-
dc.subject.keywordAuthorGPGPU-
dc.subject.keywordAuthorcomplexity-
dc.subject.keywordAuthormerging-
dc.subject.keywordAuthorsorting-
dc.identifier.urlhttps://www.jstage.jst.go.jp/article/transinf/E95.D/12/E95.D_2769/_article-
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