Investigation of Vertical Channel Architecture for Bulk Erase Operation in Three-Dimensional NAND Flash Memory

Abstract

A bit-cost scalable (BiCS) technology using a bulk erasing method instead of the conventional erase operation using gate-induced drain leakage (GIDL) is proposed to realize better cell characteristics and process feasibility for three-dimensional (3D) NAND flash memory. This has an additional electrode layer for a bulk erase operation in the middle of a vertical string cell. Here, we confirmed that this structure using an additional electrode provides good program and erasing speed by simulation. Furthermore, junction engineering is performed to realize a polysilicon layer of the flat plate type as a bulk electrode for better design feasibility. From this result, we expect that a bulk erasable BiCS technology using a flat plate erase electrode can be a candidate 3D NAND flash memory technology.