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Executing synchronous dataflow graphs on a SPM-based multicore architecture
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Choi, Junchul | - |
| dc.contributor.author | Oh, Hyunok | - |
| dc.contributor.author | Kim, Sungchan | - |
| dc.contributor.author | Ha, Soonhoi | - |
| dc.date.accessioned | 2022-07-16T15:15:50Z | - |
| dc.date.available | 2022-07-16T15:15:50Z | - |
| dc.date.issued | 2012-06 | - |
| dc.identifier.issn | 0738-100X | - |
| dc.identifier.issn | 0146-7123 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/165488 | - |
| dc.description.abstract | In this paper we are concerned about executing synchronous dataflow (SDF) applications on a multicore architecture where a core has a limited size of scratchpad memory (SPM). Unlike traditional multi-processor scheduling of SDF graphs, we consider the SPM size limitation that incurs code and data overlay overhead. Since the scheduling problem is intractable, we propose an EA(evolutionary algorithm)-based technique. To hide memory latency, prefetching is aggressively performed in the proposed technique. The experimental results show that our approach reduces the overlay overhead significantly compared to a non-optimized approach and the previous approach. | - |
| dc.format.extent | 8 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.title | Executing synchronous dataflow graphs on a SPM-based multicore architecture | - |
| dc.type | Article | - |
| dc.identifier.doi | 10.1145/2228360.2228480 | - |
| dc.identifier.scopusid | 2-s2.0-84863545495 | - |
| dc.identifier.bibliographicCitation | Proceedings - Design Automation Conference, pp 664 - 671 | - |
| dc.citation.title | Proceedings - Design Automation Conference | - |
| dc.citation.startPage | 664 | - |
| dc.citation.endPage | 671 | - |
| dc.type.docType | Conference Paper | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.subject.keywordPlus | Multi processor scheduling | - |
| dc.subject.keywordPlus | Multicore architectures | - |
| dc.subject.keywordPlus | Prefetching | - |
| dc.subject.keywordPlus | Scratch pad memory | - |
| dc.subject.keywordPlus | Synchronous Dataflow | - |
| dc.subject.keywordPlus | Computer aided design | - |
| dc.subject.keywordPlus | Response time (computer systems) | - |
| dc.subject.keywordPlus | Scheduling | - |
| dc.subject.keywordPlus | Software architecture | - |
| dc.subject.keywordPlus | Multiprocessing systems | - |
| dc.subject.keywordAuthor | memory overlay | - |
| dc.subject.keywordAuthor | multicore architecture | - |
| dc.subject.keywordAuthor | multiprocessor scheduling | - |
| dc.subject.keywordAuthor | prefetching | - |
| dc.subject.keywordAuthor | scratch pad memory | - |
| dc.subject.keywordAuthor | synchronous dataflow | - |
| dc.identifier.url | https://dl.acm.org/doi/10.1145/2228360.2228480 | - |
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