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다중화된 곱셈기로 구현된 델타-시그마 A/D 컨버터용 데시메이션 필터
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 김태영 | - |
| dc.contributor.author | 박상규 | - |
| dc.date.accessioned | 2022-07-16T18:12:19Z | - |
| dc.date.available | 2022-07-16T18:12:19Z | - |
| dc.date.created | 2021-05-13 | - |
| dc.date.issued | 2011-11 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/167101 | - |
| dc.description.abstract | An e conomical implementation method of multi-rate multi-stage decimation filter is presented. The filter is composed of a CIC filter stage, which decimates large data rate without any multipliers, and cascaded half-band filter stages with optimized multipliers usage. This filter was successfully applied to the decimation of delta-sigma modulator output. | - |
| dc.language | 한국어 | - |
| dc.language.iso | ko | - |
| dc.publisher | 대한전자공학회 | - |
| dc.title | 다중화된 곱셈기로 구현된 델타-시그마 A/D 컨버터용 데시메이션 필터 | - |
| dc.title.alternative | Multiplier Optimized Implementation of Decimation Filter for Delta-Sigma ADC | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | 박상규 | - |
| dc.identifier.bibliographicCitation | 2011년 대한전자공학회 추계학술대회 논문집, no. , pp.89 - 90 | - |
| dc.relation.isPartOf | 2011년 대한전자공학회 추계학술대회 논문집 | - |
| dc.citation.title | 2011년 대한전자공학회 추계학술대회 논문집 | - |
| dc.citation.startPage | 89 | - |
| dc.citation.endPage | 90 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Proceeding | - |
| dc.description.journalClass | 2 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | other | - |
| dc.identifier.url | https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE02338861 | - |
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Collections - 서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles
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Related Researcher
- Park, Sang Gyu
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)