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Effect of the trap density and distribution of the silicon nitride layer on the retention characteristics of charge trap flash memory devices

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dc.contributor.authorYou, Joo Hyung-
dc.contributor.authorKim, Hyun Woo-
dc.contributor.authorKim, Dong Hun-
dc.contributor.authorKim, Tae Whan-
dc.contributor.authorLee, Keun Woo-
dc.date.accessioned2022-07-16T19:17:49Z-
dc.date.available2022-07-16T19:17:49Z-
dc.date.created2021-05-11-
dc.date.issued2011-09-
dc.identifier.issn0000-0000-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/167724-
dc.description.abstractThe trap distribution in the silicon-nitride layer, which was estimated by using experimental results, was used to clarify the retention characteristics of TaN-Al2O3-Si3N4-SiO2-Si (TANOS) memory devices. The dependence of the trap density and distribution of the silicon nitride layer on the retention characteristics in TANOS memory devices was investigated by using the two-coupled rate equations together with the Shockley- Reed statistics. Simulation results showed that the retention characteristics in TANOS memory devices increased with increasing trap density near and above the Fermi-level in the silicon-nitride layer. The simulation results for the retention characteristics of TANOS memory devices were in reasonable agreement with the experimental results. These observations can help improve understanding of the retention mechanisms and the reliability problems in charge trap flash (CTF) memory devices.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-
dc.titleEffect of the trap density and distribution of the silicon nitride layer on the retention characteristics of charge trap flash memory devices-
dc.typeArticle-
dc.contributor.affiliatedAuthorKim, Tae Whan-
dc.identifier.doi10.1109/SISPAD.2011.6035085-
dc.identifier.scopusid2-s2.0-80054985275-
dc.identifier.bibliographicCitationInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD, pp.199 - 202-
dc.relation.isPartOfInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD-
dc.citation.titleInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD-
dc.citation.startPage199-
dc.citation.endPage202-
dc.type.rimsART-
dc.type.docTypeConference Paper-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscopus-
dc.subject.keywordPlusCharge trap flash memories-
dc.subject.keywordPlusRate equations-
dc.subject.keywordPlusReliability problems-
dc.subject.keywordPlusRetention characteristics-
dc.subject.keywordPlusRetention mechanism-
dc.subject.keywordPlusSimulation result-
dc.subject.keywordPlusTANOS flash memory-
dc.subject.keywordPlusTrap density-
dc.subject.keywordPlusTrap distributions-
dc.subject.keywordPlusCharge trapping-
dc.subject.keywordPlusEquipment-
dc.subject.keywordPlusSemiconducting silicon-
dc.subject.keywordPlusSemiconductor devices-
dc.subject.keywordPlusSilicon nitride-
dc.subject.keywordPlusSilicon oxides-
dc.subject.keywordPlusTantalum compounds-
dc.subject.keywordPlusFlash memory-
dc.subject.keywordAuthorretention characteristics-
dc.subject.keywordAuthorsilicon nitride-
dc.subject.keywordAuthorTANOS flash memory-
dc.subject.keywordAuthortrap distribution-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/6035085-
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