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Decrease in Interference Effects between Cells for Metal-Oxide-Nitride-Oxide-Silicon NAND Flash Memory Devices with Metal Spacer Layers
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Sung Ho | - |
| dc.contributor.author | You, Joo Hyung | - |
| dc.contributor.author | Kim, Tae Whan | - |
| dc.date.accessioned | 2022-07-16T19:55:57Z | - |
| dc.date.available | 2022-07-16T19:55:57Z | - |
| dc.date.issued | 2011-07 | - |
| dc.identifier.issn | 0021-4922 | - |
| dc.identifier.issn | 1347-4065 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/168049 | - |
| dc.description.abstract | Nanoscale metal-oxide-nitride-oxide-silicon (MONOS) NAND flash memory devices with a metal spacer layer were designed to increase the fringing field and the coupling ratio of the control gate and to decrease the interference effects between the cells. The simulation results showed that the drain current and the threshold voltage shift of the MONOS NAND flash memory devices utilizing a metal spacer increased owing to the increase in the fringing field and the coupling ratio. The electric field on the channel surface of the memory devices with a metal spacer layer increased, indicative of the achievement of the maximum fringing field effect, resulting in an increase in the drain current. The simulation results showed that the interference effects for the memory devices utilizing a metal spacer decreased resulting from the shielding of the electric field between neighboring cells. | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | IOP Publishing Ltd | - |
| dc.title | Decrease in Interference Effects between Cells for Metal-Oxide-Nitride-Oxide-Silicon NAND Flash Memory Devices with Metal Spacer Layers | - |
| dc.type | Article | - |
| dc.publisher.location | 영국 | - |
| dc.identifier.doi | 10.1143/JJAP.50.074301 | - |
| dc.identifier.scopusid | 2-s2.0-79960673846 | - |
| dc.identifier.wosid | 000292878200065 | - |
| dc.identifier.bibliographicCitation | Japanese Journal of Applied Physics, v.50, no.7 | - |
| dc.citation.title | Japanese Journal of Applied Physics | - |
| dc.citation.volume | 50 | - |
| dc.citation.number | 7 | - |
| dc.type.docType | Article | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | sci | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Physics | - |
| dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
| dc.subject.keywordPlus | FLOATING-GATE | - |
| dc.subject.keywordPlus | V-TH | - |
| dc.subject.keywordPlus | PERFORMANCE | - |
| dc.subject.keywordPlus | TRANSISTOR | - |
| dc.identifier.url | https://iopscience.iop.org/article/10.1143/JJAP.50.074301 | - |
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