A task remapping technique for reliable multi-core embedded systems
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Chanhee | - |
dc.contributor.author | Kim, Hokeun | - |
dc.contributor.author | Park, Hae-woo | - |
dc.contributor.author | Kim, Sungchan. | - |
dc.contributor.author | Oh, Hyunok | - |
dc.contributor.author | Ha, Soonhoi | - |
dc.date.accessioned | 2022-12-20T11:23:25Z | - |
dc.date.available | 2022-12-20T11:23:25Z | - |
dc.date.created | 2022-09-16 | - |
dc.date.issued | 2010-10 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/173569 | - |
dc.description.abstract | With the continuous scaling of semiconductor technology, the life-time of circuit is decreasing so that processor failure becomes an important issue in MPSoC design. A software solution to tolerate run-time processor failure is to migrate tasks from the failed processors to the live processors when failure occurs. Previous works on run-time task migration usually aim to minimize the migration overhead with or without a given latency constraint. For streaming applications, however, it is more important to minimize the throughput degradation than the migration overhead or the latency. Hence, we propose a task remapping technique to minimize the throughput degradation assuming that the migration overhead can be amortized safely. The target multi-core system assumed in this paper consists of processor pools and each pool consists of homogeneous processors. The proposed technique is based on an intensive compile-time analysis for all possible failure scenarios. It involves the following steps; 1) Determine the static mapping of tasks onto the live processors, aiming to minimize the throughput degradation: 2) Find an optimal processor-to-processor mapping to minimize the task migration overhead: and 3) Store the resultant task remapping information that includes task mapping and processor-to-processor mapping results. Since the task remapping information is pre-computed at compile-time for all possible failure scenarios, it should be efficiently represented and stored. At run-time, we simply remap the tasks following the compile-time decision. We examine the scalability of the proposed technique on both space and run-time overhead for compile-time analysis varying the number of failed processors. Through intensive experiments, we show that the proposed technique outperforms the previous works with respect to application throughput. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.title | A task remapping technique for reliable multi-core embedded systems | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Oh, Hyunok | - |
dc.identifier.doi | 10.1145/1878961.1879014 | - |
dc.identifier.scopusid | 2-s2.0-78650631362 | - |
dc.identifier.bibliographicCitation | Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010, pp.307 - 316 | - |
dc.relation.isPartOf | Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010 | - |
dc.citation.title | Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010 | - |
dc.citation.startPage | 307 | - |
dc.citation.endPage | 316 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | Compile time | - |
dc.subject.keywordPlus | Homogeneous processors | - |
dc.subject.keywordPlus | Latency constraints | - |
dc.subject.keywordPlus | Life-times | - |
dc.subject.keywordPlus | Multi core | - |
dc.subject.keywordPlus | Multi-core embedded systems | - |
dc.subject.keywordPlus | Multi-core systems | - |
dc.subject.keywordPlus | Processor failures | - |
dc.subject.keywordPlus | Remapping | - |
dc.subject.keywordPlus | Runtimes | - |
dc.subject.keywordPlus | Semiconductor technology | - |
dc.subject.keywordPlus | Software solution | - |
dc.subject.keywordPlus | Static mapping | - |
dc.subject.keywordPlus | Streaming applications | - |
dc.subject.keywordPlus | Task mapping | - |
dc.subject.keywordPlus | Task migration | - |
dc.subject.keywordPlus | Throughput degradation | - |
dc.subject.keywordPlus | static task mapping | - |
dc.subject.keywordPlus | Degradation | - |
dc.subject.keywordPlus | Lakes | - |
dc.subject.keywordPlus | Mapping | - |
dc.subject.keywordPlus | Quality assurance | - |
dc.subject.keywordPlus | Semiconductor device manufacture | - |
dc.subject.keywordPlus | Throughput | - |
dc.subject.keywordPlus | Continuous time systems | - |
dc.subject.keywordPlus | Microprocessor chips | - |
dc.subject.keywordPlus | Software reliability | - |
dc.subject.keywordPlus | Embedded systems | - |
dc.subject.keywordAuthor | Multi-core embedded systems | - |
dc.subject.keywordAuthor | Reliability | - |
dc.subject.keywordAuthor | Static task mapping | - |
dc.identifier.url | https://dl.acm.org/doi/10.1145/1878961.1879014 | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
222, Wangsimni-ro, Seongdong-gu, Seoul, 04763, Korea+82-2-2220-1365
COPYRIGHT © 2021 HANYANG UNIVERSITY.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.