Nanoscale Two-Bit/Cell NAND Silicon-Oxide-Nitride-Oxide-Silicon Devices Designed on Fully Depleted Silicon-on-Insulator Substrates
DC Field | Value | Language |
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dc.contributor.author | Kim, Hyun Joo | - |
dc.contributor.author | You, Joo Hyung | - |
dc.contributor.author | Kwack, Kae Dal | - |
dc.contributor.author | Kim, Tae Whan | - |
dc.date.accessioned | 2022-12-20T15:48:07Z | - |
dc.date.available | 2022-12-20T15:48:07Z | - |
dc.date.created | 2022-08-27 | - |
dc.date.issued | 2010-09 | - |
dc.identifier.issn | 0021-4922 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/174139 | - |
dc.description.abstract | Nanoscale 2-bit/cell NAND silicon-oxide-nitride-oxide-silicon (SONOS) memory devices with two separated control gates utilizing a fully depleted silicon-on-insulator (SOI) structure were designed. The program and erase characteristics of the proposed unique nanoscale 2-bit/cell NAND SONOS memory devices were simulated using technology computer-aided design tools. Simulation results showed that the leakage current in the subthreshold region and the subthreshold swing for the nanoscale 2-bit/cell NAND SONOS memory devices were decreased by utilizing a SOI structure. The initial threshold voltage of the nanoscale 2-bit/cell NAND SONOS memory devices with a SOI structure was larger than that of conventional SONOS devices without a SOI structure, indicative of a decrease in leakage current. Simulation results showed that the short-channel effects in the nanoscale 2-bit/cell NAND SONOS memory devices decreased in magnitude owing to a larger effective channel length. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IOP PUBLISHING LTD | - |
dc.title | Nanoscale Two-Bit/Cell NAND Silicon-Oxide-Nitride-Oxide-Silicon Devices Designed on Fully Depleted Silicon-on-Insulator Substrates | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Tae Whan | - |
dc.identifier.doi | 10.1143/JJAP.49.094201 | - |
dc.identifier.scopusid | 2-s2.0-78049414695 | - |
dc.identifier.wosid | 000282136400033 | - |
dc.identifier.bibliographicCitation | JAPANESE JOURNAL OF APPLIED PHYSICS, v.49, no.9, pp.1 - 4 | - |
dc.relation.isPartOf | JAPANESE JOURNAL OF APPLIED PHYSICS | - |
dc.citation.title | JAPANESE JOURNAL OF APPLIED PHYSICS | - |
dc.citation.volume | 49 | - |
dc.citation.number | 9 | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 4 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | FLASH MEMORY | - |
dc.subject.keywordPlus | HIGH-SPEED | - |
dc.identifier.url | https://iopscience.iop.org/article/10.1143/JJAP.49.094201 | - |
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