Relationship between Buffer Replacement Policy and Flash Translation Layer Mapping Algorithm

Abstract

Because a Flash Translation Layer (FTL), which enables an NAND flash memory-based storage system to be used as a block device, processes read requests that could not be served from the buffer and write requests for pages that were evicted from the buffer by the buffer replacement algorithm, an FTL algorithm has a close relationship with the buffer replacement algorithm. In this research, we implemented an I/O performance evaluation tool, IPSiNS, which simulates both the buffer replacement and FTL algorithms simultaneously. Using IPSiNS, we analyzed the relationships between buffer replacement algorithms and FTL mapping algorithms that could be extracted through the experiments using IPSiNS. We found that the page hit ratio in the buffer cannot be the only performance metric for evaluating the overall I/O performance of the system. Furthermore, we found that the number of write requests to the flash memory does not determine the exact performance of the storage device. It is therefore necessary to devise a novel FTL-aware buffer replacement algorithm, which takes the behavior of the underlying FTL algorithm into consideration.