Detailed Information
Cited 0 time in 
Cited 0 time in 
Cited 0 time in
Metadata Downloads
Multilevel Dual-Channel NAND Flash Memories with High Read and Program Verifying Speeds Utilizing Asymmetrically-Doped Channel Regions
Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, Joung Woo | - |
| dc.contributor.author | You, Joo Hyung | - |
| dc.contributor.author | Jang, Sang Hyun | - |
| dc.contributor.author | Dal Kwack, Kae | - |
| dc.contributor.author | Kim, Tae Whan | - |
| dc.date.accessioned | 2022-12-20T17:57:28Z | - |
| dc.date.available | 2022-12-20T17:57:28Z | - |
| dc.date.created | 2022-08-27 | - |
| dc.date.issued | 2010-05 | - |
| dc.identifier.issn | 0916-8524 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/175027 | - |
| dc.description.abstract | The multilevel dual-channel (MLDC) not-AND (NAND) flash memories cell structures with asymmetrically-doped channel regions between the source and the drain were proposed to enhance read and program verifying speeds. The channel structure of the MLDC flash memories consisted of two different doping channel regions. The technical computer aided design simulation results showed that the designed MLDC NAND flash cell with asymmetrically-doped channel regions provided the highspeed multilevel reading with a wider current sensing margin and the highspeed program verifying due to the sensing of the discrete current levels. The proposed unique MLDC NAND flash memory device can be used to increase read and program verifying speed. | - |
| dc.language | 영어 | - |
| dc.language.iso | en | - |
| dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
| dc.title | Multilevel Dual-Channel NAND Flash Memories with High Read and Program Verifying Speeds Utilizing Asymmetrically-Doped Channel Regions | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Kim, Tae Whan | - |
| dc.identifier.doi | 10.1587/transele.E93.C.654 | - |
| dc.identifier.scopusid | 2-s2.0-77951802085 | - |
| dc.identifier.wosid | 000281341500024 | - |
| dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON ELECTRONICS, v.E93C, no.5, pp.654 - 657 | - |
| dc.relation.isPartOf | IEICE TRANSACTIONS ON ELECTRONICS | - |
| dc.citation.title | IEICE TRANSACTIONS ON ELECTRONICS | - |
| dc.citation.volume | E93C | - |
| dc.citation.number | 5 | - |
| dc.citation.startPage | 654 | - |
| dc.citation.endPage | 657 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Article | - |
| dc.description.journalClass | 1 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.subject.keywordPlus | ARCHITECTURE | - |
| dc.subject.keywordAuthor | NAND flash memory | - |
| dc.subject.keywordAuthor | multilevel dual-channel | - |
| dc.subject.keywordAuthor | high-speed multilevel reading | - |
| dc.subject.keywordAuthor | current sensing | - |
| dc.subject.keywordAuthor | high-speed program verifying | - |
| dc.identifier.url | https://www.jstage.jst.go.jp/article/transele/E93.C/5/E93.C_5_654/_article | - |
- Files in This Item
- Go to Link
- Appears in
Collections - 서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.