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Reduced distribution of threshold voltage shift in double layer NiSi 2 nanocrystals for nano-floating gate memory applications
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Choi, Sung-Jin | - |
| dc.contributor.author | Lee, Jun-Hyuk | - |
| dc.contributor.author | Kim, Dong-Hyoun | - |
| dc.contributor.author | Oh, Seul-Ki | - |
| dc.contributor.author | Song, Wangyu | - |
| dc.contributor.author | Choi, Seon-Jun | - |
| dc.contributor.author | Lee, Seung-Beck | - |
| dc.date.accessioned | 2022-12-20T18:40:20Z | - |
| dc.date.available | 2022-12-20T18:40:20Z | - |
| dc.date.created | 2022-09-16 | - |
| dc.date.issued | 2010-03 | - |
| dc.identifier.issn | 0000-0000 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/175297 | - |
| dc.description.abstract | We report on the fabrication and C-V characteristics of double layer NiSi2 nanocrystals (NCs) with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. The variation in threshold voltage shift ΔVTH) was measured for samples at different stress voltages. The ΔVTH increased with applied program voltage from 1.0 V at 3 V to 2.3 V at 7 V. Compared with SiO 2, ΔVTH is reduced to 0.2-0.4 V in each program voltages demonstrating possible multi-level-cell (MLC) operation. | - |
| dc.language | 영어 | - |
| dc.language.iso | en | - |
| dc.publisher | IEEE | - |
| dc.title | Reduced distribution of threshold voltage shift in double layer NiSi 2 nanocrystals for nano-floating gate memory applications | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Lee, Seung-Beck | - |
| dc.identifier.doi | 10.1109/INEC.2010.5424920 | - |
| dc.identifier.scopusid | 2-s2.0-77951661105 | - |
| dc.identifier.bibliographicCitation | INEC 2010 - 2010 3rd International Nanoelectronics Conference, Proceedings, pp.1246 - 1247 | - |
| dc.relation.isPartOf | INEC 2010 - 2010 3rd International Nanoelectronics Conference, Proceedings | - |
| dc.citation.title | INEC 2010 - 2010 3rd International Nanoelectronics Conference, Proceedings | - |
| dc.citation.startPage | 1246 | - |
| dc.citation.endPage | 1247 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Conference Paper | - |
| dc.description.journalClass | 1 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.subject.keywordPlus | Applied programs | - |
| dc.subject.keywordPlus | C-V characteristic | - |
| dc.subject.keywordPlus | Double layers | - |
| dc.subject.keywordPlus | Multi-level | - |
| dc.subject.keywordPlus | Nanofloating gate memory | - |
| dc.subject.keywordPlus | Program voltage | - |
| dc.subject.keywordPlus | Stress voltages | - |
| dc.subject.keywordPlus | Threshold voltage shifts | - |
| dc.subject.keywordPlus | Tunnel barrier | - |
| dc.subject.keywordPlus | Nanocrystals | - |
| dc.subject.keywordPlus | Nanoelectronics | - |
| dc.subject.keywordPlus | Silicon compounds | - |
| dc.subject.keywordPlus | Threshold voltage | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/5424920 | - |
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Related Researcher
- Lee, Seung Beck
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)