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Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory

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dc.contributor.authorSong, Youngsun-
dc.contributor.authorPark, Ki-Tae-
dc.contributor.authorKang, Myounggon-
dc.contributor.authorSong, Yunheub-
dc.contributor.authorLee, Sungsoo-
dc.contributor.authorLim, Youngho-
dc.contributor.authorSuh, Kang-Deog-
dc.date.accessioned2022-12-20T18:46:31Z-
dc.date.available2022-12-20T18:46:31Z-
dc.date.created2022-08-27-
dc.date.issued2010-03-
dc.identifier.issn0916-8524-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/175354-
dc.description.abstractA boosted bit line program scheme is proposed tor low operating voltage in the (MLC) NAND Hash memory Our BL to BL boosting scheme. which uses the BL coupling capacitance. is applied to achieve a higher channel potential than is possible with V-cc. so that the V-pass window margin is improved by up to 59% in 40 nm MLC NAND flash memory with 2 7 V V-cc In the case of 1 8 V V-cc, the margin of the proposed scheme is 12% higher than one of the conventional schemes at 2 7 V V-cc.-
dc.language영어-
dc.language.isoen-
dc.publisherIEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG-
dc.titleBoosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory-
dc.typeArticle-
dc.contributor.affiliatedAuthorSong, Yunheub-
dc.identifier.doi10.1587/transele.E93.C.423-
dc.identifier.scopusid2-s2.0-77950443223-
dc.identifier.wosid000276760400028-
dc.identifier.bibliographicCitationIEICE TRANSACTIONS ON ELECTRONICS, v.E93C, no.3, pp.423 - 425-
dc.relation.isPartOfIEICE TRANSACTIONS ON ELECTRONICS-
dc.citation.titleIEICE TRANSACTIONS ON ELECTRONICS-
dc.citation.volumeE93C-
dc.citation.number3-
dc.citation.startPage423-
dc.citation.endPage425-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusCapacitance-
dc.subject.keywordPlusMemory architecture-
dc.subject.keywordPlusNAND circuits-
dc.subject.keywordPlusBit lines-
dc.subject.keywordPlusBoosted channel-
dc.subject.keywordPlusConventional schemes-
dc.subject.keywordPlusCoupling capacitance-
dc.subject.keywordPlusLow operating voltage-
dc.subject.keywordPlusMulti level cell (MLC)-
dc.subject.keywordPlusNAND flash memory-
dc.subject.keywordPlusVpass window margin-
dc.subject.keywordPlusFlash memory-
dc.subject.keywordAuthorbit line-
dc.subject.keywordAuthorcoupling capacitance-
dc.subject.keywordAuthorV-pass window margin-
dc.subject.keywordAuthorboosted channel-
dc.identifier.urlhttps://www.jstage.jst.go.jp/article/transele/E93.C/3/E93.C_3_423/_article-
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