Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory
DC Field | Value | Language |
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dc.contributor.author | Song, Youngsun | - |
dc.contributor.author | Park, Ki-Tae | - |
dc.contributor.author | Kang, Myounggon | - |
dc.contributor.author | Song, Yunheub | - |
dc.contributor.author | Lee, Sungsoo | - |
dc.contributor.author | Lim, Youngho | - |
dc.contributor.author | Suh, Kang-Deog | - |
dc.date.accessioned | 2022-12-20T18:46:31Z | - |
dc.date.available | 2022-12-20T18:46:31Z | - |
dc.date.created | 2022-08-27 | - |
dc.date.issued | 2010-03 | - |
dc.identifier.issn | 0916-8524 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/175354 | - |
dc.description.abstract | A boosted bit line program scheme is proposed tor low operating voltage in the (MLC) NAND Hash memory Our BL to BL boosting scheme. which uses the BL coupling capacitance. is applied to achieve a higher channel potential than is possible with V-cc. so that the V-pass window margin is improved by up to 59% in 40 nm MLC NAND flash memory with 2 7 V V-cc In the case of 1 8 V V-cc, the margin of the proposed scheme is 12% higher than one of the conventional schemes at 2 7 V V-cc. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.title | Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Song, Yunheub | - |
dc.identifier.doi | 10.1587/transele.E93.C.423 | - |
dc.identifier.scopusid | 2-s2.0-77950443223 | - |
dc.identifier.wosid | 000276760400028 | - |
dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON ELECTRONICS, v.E93C, no.3, pp.423 - 425 | - |
dc.relation.isPartOf | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.citation.title | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.citation.volume | E93C | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 423 | - |
dc.citation.endPage | 425 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | Capacitance | - |
dc.subject.keywordPlus | Memory architecture | - |
dc.subject.keywordPlus | NAND circuits | - |
dc.subject.keywordPlus | Bit lines | - |
dc.subject.keywordPlus | Boosted channel | - |
dc.subject.keywordPlus | Conventional schemes | - |
dc.subject.keywordPlus | Coupling capacitance | - |
dc.subject.keywordPlus | Low operating voltage | - |
dc.subject.keywordPlus | Multi level cell (MLC) | - |
dc.subject.keywordPlus | NAND flash memory | - |
dc.subject.keywordPlus | Vpass window margin | - |
dc.subject.keywordPlus | Flash memory | - |
dc.subject.keywordAuthor | bit line | - |
dc.subject.keywordAuthor | coupling capacitance | - |
dc.subject.keywordAuthor | V-pass window margin | - |
dc.subject.keywordAuthor | boosted channel | - |
dc.identifier.url | https://www.jstage.jst.go.jp/article/transele/E93.C/3/E93.C_3_423/_article | - |
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