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Symmetric Adiabatic Logic Circuits against Differential Power Analysis
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Choi, Byong-Deok | - |
| dc.contributor.author | Kim, Kyung Eun | - |
| dc.contributor.author | Chung, Ki-Seok | - |
| dc.contributor.author | Kim, Dong Kyue | - |
| dc.date.accessioned | 2022-12-20T19:09:32Z | - |
| dc.date.available | 2022-12-20T19:09:32Z | - |
| dc.date.issued | 2010-02 | - |
| dc.identifier.issn | 1225-6463 | - |
| dc.identifier.issn | 2233-7326 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/175498 | - |
| dc.description.abstract | We investigate the possibility of using adiabatic logic as a countermeasure against differential power analysis (DPA) style attacks to make use of its energy efficiency. Like other dual-rail logics, adiabatic logic exhibits a current dependence on input data, which makes the system vulnerable to DPA. To resolve this issue, we propose a symmetric adiabatic logic in which the discharge paths are symmetric for data-independent parasitic capacitance, and the charges are shared between the output nodes and between the internal nodes, respective v to prevent the circuit from depending on the previous input data. | - |
| dc.format.extent | 3 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | 한국전자통신연구원 | - |
| dc.title | Symmetric Adiabatic Logic Circuits against Differential Power Analysis | - |
| dc.type | Article | - |
| dc.publisher.location | 대한민국 | - |
| dc.identifier.doi | 10.4218/etrij.10.0209.0247 | - |
| dc.identifier.scopusid | 2-s2.0-77249175672 | - |
| dc.identifier.wosid | 000274705000025 | - |
| dc.identifier.bibliographicCitation | ETRI Journal, v.32, no.1, pp 166 - 168 | - |
| dc.citation.title | ETRI Journal | - |
| dc.citation.volume | 32 | - |
| dc.citation.number | 1 | - |
| dc.citation.startPage | 166 | - |
| dc.citation.endPage | 168 | - |
| dc.type.docType | Article | - |
| dc.identifier.kciid | ART001418725 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | sci | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.description.journalRegisteredClass | kci | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalResearchArea | Telecommunications | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalWebOfScienceCategory | Telecommunications | - |
| dc.subject.keywordPlus | Electric power supplies to apparatus | - |
| dc.subject.keywordPlus | Energy efficiency | - |
| dc.subject.keywordPlus | Input output prograLogic circuitsms | - |
| dc.subject.keywordPlus | Signal analysis | - |
| dc.subject.keywordPlus | Switching circuits | - |
| dc.subject.keywordPlus | Adiabatic logic | - |
| dc.subject.keywordPlus | Adiabatic logic circuits | - |
| dc.subject.keywordPlus | Current dependence | - |
| dc.subject.keywordPlus | Differential power analysis | - |
| dc.subject.keywordPlus | Discharge path | - |
| dc.subject.keywordPlus | Dual-rail logic | - |
| dc.subject.keywordPlus | Input datas | - |
| dc.subject.keywordPlus | Internal nodes | - |
| dc.subject.keywordPlus | Low-power consumption | - |
| dc.subject.keywordPlus | Parasitic capacitance | - |
| dc.subject.keywordPlus | Side-channel attacks | - |
| dc.subject.keywordAuthor | Side channel attack (SCA) | - |
| dc.subject.keywordAuthor | differential power analysis (DPA) | - |
| dc.subject.keywordAuthor | adiabatic logic | - |
| dc.subject.keywordAuthor | low power consumption | - |
| dc.identifier.url | https://onlinelibrary.wiley.com/doi/abs/10.4218/etrij.10.0209.0247 | - |
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