Simulation of Nanoscale Two-Bit Not-And-type Silicon-Oxide-Nitride-Oxide-Silicon Nonvolatile Memory Devices with a Separated Double-Gate Fin Field Effect Transistor Structure Containing Different Tunneling Oxide Thicknesses
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Oh, Se Woong | - |
dc.contributor.author | Park, Sang Su | - |
dc.contributor.author | Kim, Dong Hun | - |
dc.contributor.author | Kim, Hyun Woo | - |
dc.contributor.author | Kim, Tate Whan | - |
dc.date.accessioned | 2022-12-20T21:56:53Z | - |
dc.date.available | 2022-12-20T21:56:53Z | - |
dc.date.created | 2022-08-26 | - |
dc.date.issued | 2009-06 | - |
dc.identifier.issn | 0021-4922 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/176699 | - |
dc.description.abstract | Not-and (NAND)-type silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory (NVM) devices with a separated double-gate (SDG) Fin field effect transistor structure were proposed to reduce the unit cell size of such memory devices and increase their memory density in comparison with that of conventional NVM devices. The proposed memory device consisted of a pair of control gates separated along the length of the Fin channel direction. Each SDG had a different thickness of the tunneling oxide to operate the proposed memory device as a two-bit/cell device. A technology computer-aided design simulation was performed to investigate the program/erase and two-bit characteristics. The simulation results show that the proposed devices can be used to increase the scaling down capability and charge storage density of NAND-type SONOS NVM devices. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IOP Publishing Ltd | - |
dc.title | Simulation of Nanoscale Two-Bit Not-And-type Silicon-Oxide-Nitride-Oxide-Silicon Nonvolatile Memory Devices with a Separated Double-Gate Fin Field Effect Transistor Structure Containing Different Tunneling Oxide Thicknesses | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Tate Whan | - |
dc.identifier.doi | 10.1143/JJAP.48.06FD12 | - |
dc.identifier.scopusid | 2-s2.0-70249085931 | - |
dc.identifier.wosid | 000267674600036 | - |
dc.identifier.bibliographicCitation | JAPANESE JOURNAL OF APPLIED PHYSICS, v.48, no.6, pp.1 - 4 | - |
dc.relation.isPartOf | JAPANESE JOURNAL OF APPLIED PHYSICS | - |
dc.citation.title | JAPANESE JOURNAL OF APPLIED PHYSICS | - |
dc.citation.volume | 48 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 4 | - |
dc.type.rims | ART | - |
dc.type.docType | Article; Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | NAND FLASH MEMORY | - |
dc.subject.keywordPlus | SONOS MEMORY | - |
dc.subject.keywordPlus | CELL | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.identifier.url | https://iopscience.iop.org/article/10.1143/JJAP.48.06FD12 | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
222, Wangsimni-ro, Seongdong-gu, Seoul, 04763, Korea+82-2-2220-1365
COPYRIGHT © 2021 HANYANG UNIVERSITY.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.