Design of a Latchup-Free ESD Power Clamp for Smart Power ICs

Abstract

A latchup-free design based on the lateral diffused MOS (LDMOS) adopting the "Darlington" approaches was designed. The use of Darlington configuration as the trigger circuit results in the reduction of the size of the circuit when compared to the conventional inverter driven RC-riggered MOSFET ESD power clamp circuits. The proposed clamp was fabricated using a 0.35 μm 60V BCD (Bipolar CMOS DMOS) process and the performance of the proposed clamp was successfully verified by TLP (Transmission Line Pulsing) measurements.