FPGA design and implementation of UDCM for the WiBro system
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cho, Kyongkuk | - |
dc.contributor.author | Lee, Kyungmin | - |
dc.contributor.author | Yoon, Dongweon | - |
dc.contributor.author | Lee, Wooju | - |
dc.contributor.author | Park, Sang Gyu | - |
dc.date.accessioned | 2022-12-21T01:52:31Z | - |
dc.date.available | 2022-12-21T01:52:31Z | - |
dc.date.created | 2022-09-16 | - |
dc.date.issued | 2008-07 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/178140 | - |
dc.description.abstract | In this paper, we implement the UDCM(Up Down Conversion Module) for the WiBro base station equipment RAS(Radio Access Station). It performs the digital IF (Intermediate Frequency) signal processing between a channel card and the Radio Equipments(REs). The UDCM embed on digital optic interface unit of RAS. Converting the frequency into WMHz or baseband is the main function. It filters the spurious within channel bandwidth for DownLink(DL) /UpLink(UL). Also to support the communication with the other chips or peripherals, we design the interface modules and controller. As the UDCM is optimized on the Virtex5 families, it can save the dedicated FPGA resources and lowers the development costs. Its functionality is verified using simulation tools on the RTL(Register Transfer Level) for the predefined test vector. After setting the timing constraints for the interface signals and timing verification, the UDCM downloaded into main unit. Finally, this digital unit is connected to a channel card and REs to ensure the expected performance for its reference simulation results by capturing I/Q, synchronization signals. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | FPGA design and implementation of UDCM for the WiBro system | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Yoon, Dongweon | - |
dc.contributor.affiliatedAuthor | Park, Sang Gyu | - |
dc.identifier.doi | 10.1109/ICWMC.2008.34 | - |
dc.identifier.scopusid | 2-s2.0-52049119295 | - |
dc.identifier.bibliographicCitation | Proceedings - The 4th International Conference on Wireless and Mobile Communications, ICWMC 2008, pp.404 - 408 | - |
dc.relation.isPartOf | Proceedings - The 4th International Conference on Wireless and Mobile Communications, ICWMC 2008 | - |
dc.citation.title | Proceedings - The 4th International Conference on Wireless and Mobile Communications, ICWMC 2008 | - |
dc.citation.startPage | 404 | - |
dc.citation.endPage | 408 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | Digital arithmetic | - |
dc.subject.keywordPlus | Equipment | - |
dc.subject.keywordPlus | Field programmable gate arrays (FPGA) | - |
dc.subject.keywordPlus | Interfaces (computer) | - |
dc.subject.keywordPlus | Radio equipment | - |
dc.subject.keywordPlus | Signal processing | - |
dc.subject.keywordPlus | Time measurement | - |
dc.subject.keywordPlus | Timing circuits | - |
dc.subject.keywordPlus | Base bands | - |
dc.subject.keywordPlus | Base stations | - |
dc.subject.keywordPlus | Channel bandwidths | - |
dc.subject.keywordPlus | Development costs | - |
dc.subject.keywordPlus | Digital IF | - |
dc.subject.keywordPlus | Down-conversion | - |
dc.subject.keywordPlus | Down-Link | - |
dc.subject.keywordPlus | FPGA | - |
dc.subject.keywordPlus | FPGA designs | - |
dc.subject.keywordPlus | Frequency conversion | - |
dc.subject.keywordPlus | Intermediate frequencies | - |
dc.subject.keywordPlus | International conferences | - |
dc.subject.keywordPlus | Mobile communications | - |
dc.subject.keywordPlus | OFDMA | - |
dc.subject.keywordPlus | Radio access | - |
dc.subject.keywordPlus | RAS interface | - |
dc.subject.keywordPlus | REC | - |
dc.subject.keywordPlus | RTL (register transfer level) | - |
dc.subject.keywordPlus | Simulation results | - |
dc.subject.keywordPlus | Simulation tools | - |
dc.subject.keywordPlus | Synchronization signals | - |
dc.subject.keywordPlus | Timing constraints | - |
dc.subject.keywordPlus | Timing verification | - |
dc.subject.keywordPlus | Uplink (UL) | - |
dc.subject.keywordPlus | WiBro base station | - |
dc.subject.keywordPlus | WiBro systems | - |
dc.subject.keywordPlus | Digital radio | - |
dc.subject.keywordAuthor | FPGA | - |
dc.subject.keywordAuthor | Frequency conversion | - |
dc.subject.keywordAuthor | OFDMA | - |
dc.subject.keywordAuthor | RAS interface | - |
dc.subject.keywordAuthor | REC | - |
dc.subject.keywordAuthor | WiBro base station | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/4591323 | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
222, Wangsimni-ro, Seongdong-gu, Seoul, 04763, Korea+82-2-2220-1365
COPYRIGHT © 2021 HANYANG UNIVERSITY.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.