Adaptive bit-reliability mapping for LDPCCoded high-order modulation systems
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Joo, Hyeong Gun | - |
dc.contributor.author | Shin, Dong Joon | - |
dc.contributor.author | Hong, Song Nam | - |
dc.date.accessioned | 2022-12-21T08:56:11Z | - |
dc.date.available | 2022-12-21T08:56:11Z | - |
dc.date.created | 2022-09-16 | - |
dc.date.issued | 2007-03 | - |
dc.identifier.issn | 1550-2252 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/180348 | - |
dc.description.abstract | In this paper, an adaptive bit-reliability mapping is proposed for the bit-level Chase combining in LDPCcoded high-order modulation systems. Contrary to the previously known bit-reliability mapping that assigns the information (or parity) bits to more (or less) reliable bit positions, the proposed mapping flexibly assigns codeword bits to the bit positions of various reliabilities by considering the characteristics of code and protection levels. Compared with the symbol-level Chase combining and the constellation rearrangement bit mapping, the proposed mapping gives 0.7 - 1.3 dB and 0.1 - 1.0 dB performance gain at FER = 10-3 with no additional complexity, respectively. The adaptive bit-reliability mappings are derived for various environments and the validity of them is confirmed through simulation. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | Adaptive bit-reliability mapping for LDPCCoded high-order modulation systems | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Shin, Dong Joon | - |
dc.identifier.doi | 10.1109/VETECS.2007.321 | - |
dc.identifier.scopusid | 2-s2.0-34547286385 | - |
dc.identifier.bibliographicCitation | IEEE Vehicular Technology Conference, pp.1539 - 1543 | - |
dc.relation.isPartOf | IEEE Vehicular Technology Conference | - |
dc.citation.title | IEEE Vehicular Technology Conference | - |
dc.citation.startPage | 1539 | - |
dc.citation.endPage | 1543 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | Adaptive algorithms | - |
dc.subject.keywordPlus | Binary codes | - |
dc.subject.keywordPlus | Computational complexity | - |
dc.subject.keywordPlus | Computer simulation | - |
dc.subject.keywordPlus | Bit reliability mapping | - |
dc.subject.keywordPlus | Bit-level Chase combining | - |
dc.subject.keywordPlus | High-order modulation systems | - |
dc.subject.keywordPlus | Signal encoding | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/4212749 | - |
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