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Multilevel dual-channel NAND flash memories with high-speed read and verifying program

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dc.contributor.authorKim, Jae-Ho-
dc.contributor.authorLee, Joung-Woo-
dc.contributor.authorMun, Kyung-Sik-
dc.contributor.authorKim, Tae Whan-
dc.date.accessioned2022-12-21T10:05:39Z-
dc.date.available2022-12-21T10:05:39Z-
dc.date.created2022-09-16-
dc.date.issued2006-10-
dc.identifier.issn0000-0000-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/180877-
dc.description.abstractThe multilevel dual channel (MLDC) NAND flash memory cell structures with asymmetrically-doped channel regions are proposed. The channel structures with a MLDC flash cell consisted of the two different doping channel regions. The technical computer aided design simulation results showed that the designed MLDC NAND flash cell provided the high-speed multilevel reading and program verifying due to the sensing of the discrete current levels utilizing the unique asymmetric channel structure.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-
dc.titleMultilevel dual-channel NAND flash memories with high-speed read and verifying program-
dc.typeArticle-
dc.contributor.affiliatedAuthorKim, Tae Whan-
dc.identifier.doi10.1109/NMDC.2006.4388777-
dc.identifier.scopusid2-s2.0-50249160545-
dc.identifier.bibliographicCitation2006 IEEE Nanotechnology Materials and Devices Conference, NMDC, v.1, pp.382 - 383-
dc.relation.isPartOf2006 IEEE Nanotechnology Materials and Devices Conference, NMDC-
dc.citation.title2006 IEEE Nanotechnology Materials and Devices Conference, NMDC-
dc.citation.volume1-
dc.citation.startPage382-
dc.citation.endPage383-
dc.type.rimsART-
dc.type.docTypeConference Paper-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscopus-
dc.subject.keywordPlusComputer aided design-
dc.subject.keywordPlusData storage equipment-
dc.subject.keywordPlusNAND circuits-
dc.subject.keywordPlusNanotechnology-
dc.subject.keywordPlusSpeed-
dc.subject.keywordPlusTechnology-
dc.subject.keywordPlusAsymmetric channels-
dc.subject.keywordPlusAsymmetrically-doped channel-
dc.subject.keywordPlusChannel regions-
dc.subject.keywordPlusChannel structures-
dc.subject.keywordPlusCurrent levels-
dc.subject.keywordPlusCurrent sensing-
dc.subject.keywordPlusDoped channels-
dc.subject.keywordPlusDual channels-
dc.subject.keywordPlusFlash cells-
dc.subject.keywordPlusHigh speeds-
dc.subject.keywordPlusMulti-level dual-channel-
dc.subject.keywordPlusNAND Flash-
dc.subject.keywordPlusNAND Flash memories-
dc.subject.keywordPlusReduce reading and program verifying time-
dc.subject.keywordPlusFlash memory-
dc.subject.keywordAuthorAsymmetrically-doped channel-
dc.subject.keywordAuthorCurrent sensing-
dc.subject.keywordAuthorMulti-level dual-channel-
dc.subject.keywordAuthorReduce reading and program verifying time-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/4388777-
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