Energy-Efficient Bus Encoding Techniques for Next-Generation PAM-4 DRAM Interfaces

Abstract

In this paper, we introduce effective bus data en-coding schemes for next-generation interfaces of DRAM with an analysis of their energy and lane efficiency characteristics. The Pulse-Amplitude-Modulation-4 (PAM-4) signaling technique has recently been adopted to memory interfaces due to their increased per-pin data-rate requirements. However, as the power consumption profile of PAM-4 symbols differs from that of NRZ symbols, the conventional Dynamic Bus Inversion (DBI) encoding fails to achieve an expected reduction of termination power. Therefore, this paper proposes data encoding schemes applicable to the PAM-4 memory links and compares their performances in terms of the termination energy with experimental results. We evaluate the proposed approaches by applying data encoding to DRAM memory access traces obtained from executing benchmarks on ARM/x86 ISA-based processors, including caches, simulated on the gem5 architecture simulator. The experimental results show that our advanced encoding algorithms enable us to achieve doubled data rate with minimal power consumption overhead.