Design Method of Vertical Lattice Loop Structure for Parasitic Inductance Reduction in a GaN HEMTs-based Converter
DC Field | Value | Language |
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dc.contributor.author | Yang, Si-Seok | - |
dc.contributor.author | Min, Sung-Soo | - |
dc.contributor.author | Eom, Chan-Hyeok | - |
dc.contributor.author | Kim, Rae Young | - |
dc.contributor.author | Lee, Gi-Young | - |
dc.date.accessioned | 2023-05-03T11:17:01Z | - |
dc.date.available | 2023-05-03T11:17:01Z | - |
dc.date.created | 2022-12-07 | - |
dc.date.issued | 2022-11 | - |
dc.identifier.issn | 2169-3536 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/185200 | - |
dc.description.abstract | Among the wide-bandgap devices, gallium nitride high electron mobility transistors (GaN HEMTs) are contributing to the high power density technology of power conversion systems due to their excellent physical properties. In contrast, the driving voltage and threshold voltage are relatively low compared to conventional power semiconductor devices, so a reliable circuit design is required. In this paper, a parasitic inductance reduction design method for the stable driving of GaN HEMTs is proposed. To reduce parasitic inductance, we propose a vertical lattice loop structure having multiple loops, and this method can be applied regardless of the package type and shape of GaN HEMT. For the design of the proposed vertical lattice loop structure, the reference loop is defined to minimize leakage inductance and the identical loop is vertically stacked. The proposed structure is applied 6-layer PCB design example and verified by experimental results. Furthermore, the proposed design method is applied at the buck converter, and improved efficiency is verified from 600 kHz to 1MHz switching frequency. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Design Method of Vertical Lattice Loop Structure for Parasitic Inductance Reduction in a GaN HEMTs-based Converter | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Rae Young | - |
dc.identifier.doi | 10.1109/ACCESS.2022.3220325 | - |
dc.identifier.scopusid | 2-s2.0-85141615668 | - |
dc.identifier.wosid | 000933355100001 | - |
dc.identifier.bibliographicCitation | IEEE Access, v.10, pp.117215 - 117224 | - |
dc.relation.isPartOf | IEEE Access | - |
dc.citation.title | IEEE Access | - |
dc.citation.volume | 10 | - |
dc.citation.startPage | 117215 | - |
dc.citation.endPage | 117224 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | Y | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Telecommunications | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Telecommunications | - |
dc.subject.keywordPlus | Buck converter | - |
dc.subject.keywordPlus | Design | - |
dc.subject.keywordPlus | Electron mobility | - |
dc.subject.keywordPlus | Gallium nitride | - |
dc.subject.keywordPlus | III-V semiconductors | - |
dc.subject.keywordPlus | Inductance | - |
dc.subject.keywordPlus | Printed circuit boards | - |
dc.subject.keywordPlus | Threshold voltage | - |
dc.subject.keywordPlus | Wide band gap semiconductors | - |
dc.subject.keywordPlus | Conductor | - |
dc.subject.keywordPlus | Design method | - |
dc.subject.keywordPlus | Flux cancelation | - |
dc.subject.keywordPlus | Gallium nitride high electron mobility transistor | - |
dc.subject.keywordPlus | High electron-mobility transistors | - |
dc.subject.keywordPlus | Lattice | - |
dc.subject.keywordPlus | Loop structure | - |
dc.subject.keywordPlus | Parasitic inductances | - |
dc.subject.keywordPlus | PCB layout | - |
dc.subject.keywordPlus | Vertical lattice loop | - |
dc.subject.keywordPlus | High electron mobility transistors | - |
dc.subject.keywordAuthor | Inductance | - |
dc.subject.keywordAuthor | Conductors | - |
dc.subject.keywordAuthor | Magnetic flux | - |
dc.subject.keywordAuthor | Lattices | - |
dc.subject.keywordAuthor | Gallium nitride | - |
dc.subject.keywordAuthor | MODFETs | - |
dc.subject.keywordAuthor | HEMTs | - |
dc.subject.keywordAuthor | Flux cancellation | - |
dc.subject.keywordAuthor | gallium nitride high electron mobility transistors | - |
dc.subject.keywordAuthor | parasitic inductance | - |
dc.subject.keywordAuthor | PCB layout | - |
dc.subject.keywordAuthor | vertical lattice loop | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9940951 | - |
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