Architecture-Aware Optimization of Layer Fusion for Latency-Optimal CNN Inference
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yoon, Minyong | - |
dc.contributor.author | Choi, Jungwook | - |
dc.date.accessioned | 2023-08-22T02:58:33Z | - |
dc.date.available | 2023-08-22T02:58:33Z | - |
dc.date.created | 2023-08-17 | - |
dc.date.issued | 2023-06 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/189408 | - |
dc.description.abstract | Layer fusion is an effective technique for accelerating latency-sensitive CNN inference tasks on resource-constrained accelerators that exploit distributed on-chip integrated memory-accelerator processing-in memory (PIM). However, previous research primarily focused on optimizing memory access, neglecting the significant impact of hardware architecture on latency. This study presents an analytical latency model for a 2D systolic array accelerator, taking into account various hardware factors such as array dimensions, buffer size, and bandwidth. We then investigate the influence of hardware architecture and fusion strategies, including weight and overlap reuse, on performance; these aspects are insufficiently addressed in existing access-based fusion models. By incorporating layer fusion with our proposed latency model across different architectures, dataflows, and workloads, we achieve up to a 53.1% reduction in end-to-end network latency compared to an access-based model. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Architecture-Aware Optimization of Layer Fusion for Latency-Optimal CNN Inference | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Choi, Jungwook | - |
dc.identifier.doi | 10.1109/AICAS57966.2023.10168659 | - |
dc.identifier.scopusid | 2-s2.0-85166380794 | - |
dc.identifier.bibliographicCitation | AICAS 2023 - IEEE International Conference on Artificial Intelligence Circuits and Systems, Proceeding, pp.1 - 4 | - |
dc.relation.isPartOf | AICAS 2023 - IEEE International Conference on Artificial Intelligence Circuits and Systems, Proceeding | - |
dc.citation.title | AICAS 2023 - IEEE International Conference on Artificial Intelligence Circuits and Systems, Proceeding | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 4 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | Convolutional neural networks | - |
dc.subject.keywordPlus | Data flow analysis | - |
dc.subject.keywordPlus | Memory architecture | - |
dc.subject.keywordPlus | Network architecture | - |
dc.subject.keywordPlus | Systolic arrays | - |
dc.subject.keywordPlus | Analytic cost model | - |
dc.subject.keywordPlus | Convolutional neural network | - |
dc.subject.keywordPlus | Cost models | - |
dc.subject.keywordPlus | Dataflow optimization | - |
dc.subject.keywordPlus | Hardware architecture | - |
dc.subject.keywordPlus | Latency model | - |
dc.subject.keywordPlus | Layer fusion | - |
dc.subject.keywordPlus | On chips | - |
dc.subject.keywordPlus | Optimisations | - |
dc.subject.keywordPlus | Processing-in-memory | - |
dc.subject.keywordAuthor | analytic cost model | - |
dc.subject.keywordAuthor | convolutional neural network | - |
dc.subject.keywordAuthor | dataflow optimization | - |
dc.subject.keywordAuthor | Layer fusion | - |
dc.subject.keywordAuthor | systolic array | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/10168659 | - |
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