Highly Available Packet Buffer Design With Hybrid Nonvolatile Memory
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Song, Yongwoon | - |
dc.contributor.author | Hwang, Jooyoung | - |
dc.contributor.author | Insoon, Jo | - |
dc.contributor.author | Lee, Hyukjun | - |
dc.date.accessioned | 2023-09-04T07:19:07Z | - |
dc.date.available | 2023-09-04T07:19:07Z | - |
dc.date.created | 2023-07-21 | - |
dc.date.issued | 2021-10 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/189727 | - |
dc.description.abstract | Internet routers/switches are vulnerable to system failures which require a power reset. Tremendous efforts are made to guarantee the high availability of the systems. A recent work shows that a phase change memory (PCM)-based routing lookup table can achieve high availability in the destination lookup of routers/switches. However, a packet buffer in routers/switches cannot benefit from the lookup table approach because it requires a much larger and higher-bandwidth memory system and its memory traffic is equally divided into reads and writes, while routing table accesses are mostly read-dominant. PCM can provide high availability even when the system undergoes a power reset but exhibits unacceptable write bandwidth. In this work, we propose a magnetic RAM (MRAM)/PCM-based hybrid memory packet buffer and a packet mapping method. A small MRAM combined with a large PCM can outperform the dynamic random access memory (DRAM)-based packet buffer by 28.5% or 22.4% on average for internet-mix packet traffic when optimizing only bandwidth or both bandwidth and lifetime. The proposed adaptive packet mapping method maps small packets less than a predetermined packet size threshold to MRAM for maximizing PCM bandwidth as small packets degrade row buffer locality in PCM. In addition, the mapping method dynamically changes the packet size threshold to capture the working set of packet buffering, which significantly improves PCM lifetime. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Highly Available Packet Buffer Design With Hybrid Nonvolatile Memory | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Insoon, Jo | - |
dc.identifier.doi | 10.1109/TVLSI.2021.3116272 | - |
dc.identifier.scopusid | 2-s2.0-85117293270 | - |
dc.identifier.wosid | 000712564000022 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.29, no.11, pp.2008 - 2012 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 29 | - |
dc.citation.number | 11 | - |
dc.citation.startPage | 2008 | - |
dc.citation.endPage | 2012 | - |
dc.type.rims | ART | - |
dc.type.docType | 정기학술지(Article(Perspective Article포함)) | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | Y | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer ScienceEngineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & ArchitectureEngineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | Phase change materials | - |
dc.subject.keywordAuthor | Bandwidth | - |
dc.subject.keywordAuthor | Random access memory | - |
dc.subject.keywordAuthor | Routing | - |
dc.subject.keywordAuthor | Buffer storage | - |
dc.subject.keywordAuthor | Packet loss | - |
dc.subject.keywordAuthor | Nonvolatile memory | - |
dc.subject.keywordAuthor | High availability | - |
dc.subject.keywordAuthor | hybrid memory | - |
dc.subject.keywordAuthor | nonvolatile memory | - |
dc.subject.keywordAuthor | packet buffer | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9569954 | - |
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