A Low Power Digital Logic Structure for High Resolution and High Frame Rate OLEDoS Micro Displays

Abstract

This paper proposes a digital logic circuit in the source driver for OLEDoS micro display which uses a novel data signal tree structure with clock gating logic to reduce power consumption. The proposed structure for 4096×4096 (4K) 144 Hz micro displays was verified using a CMOS 110 nm process. The power consumption was reduced by 69.6% compared to the conventional data signal tree structure, enabling a low-power design.